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Sun, 19 Sep 2021 15:01:28 -0700 (PDT) MIME-Version: 1.0 References: <20210919192104.98592-1-mcroce@linux.microsoft.com> In-Reply-To: <20210919192104.98592-1-mcroce@linux.microsoft.com> From: Matteo Croce Date: Mon, 20 Sep 2021 00:00:52 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 0/3] riscv: optimized mem* functions To: linux-riscv Cc: Linux Kernel Mailing List , linux-arch , Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Emil Renner Berthing , Akira Tsukamoto , Drew Fustini , Bin Meng , David Laight , Guo Ren , Christoph Hellwig X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210919_150131_074931_E2E5DBC7 X-CRM114-Status: GOOD ( 12.66 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Sun, Sep 19, 2021 at 9:21 PM Matteo Croce wrote: > > From: Matteo Croce > > Replace the assembly mem{cpy,move,set} with C equivalent. > > Try to access RAM with the largest bit width possible, but without > doing unaligned accesses. > > A further improvement could be to use multiple read and writes as the > assembly version was trying to do. > > Tested on a BeagleV Starlight with a SiFive U74 core, where the > improvement is noticeable. > > v3 -> v4: > - incorporate changes from proposed generic version: > https://lore.kernel.org/lkml/20210617152754.17960-1-mcroce@linux.microsoft.com/ > Sorry, the correct link is: https://lore.kernel.org/lkml/20210702123153.14093-1-mcroce@linux.microsoft.com/ -- per aspera ad upstream _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv