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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=RrhplHEW9q4d4F2AHFjRpj1n00z5X3YyF8zpTfRSZEQ=; b=IFFgrLPF3FYt9ogZLdL+sD7ugnrEcKYIw861JAgtJSwsFZDEXU6VUyEJxHNcipCkb/ 27sI6fTtK8id9k29ROBmFAaWIlDnae5+w03PoOIAgSs8K3AZjEBSBuHCff14J9+ryXeX isBuDJhw74vnA0MInjYJo2CyGoZOiL3DEvtp7ykmuA1XBAexmMOgh+Y5uSJDPYcE169o w4rEc9GzyNWUYDihJzs+xPcUPRpnAkaJunQHusa7eOeNmORe8z4QKzQlDDeb3ObCV5xd FHj2w90Lppq6GYt3sqjM79fW6LVDuZ0HROyEUxRG0rnpa6ORzWF+fnYmiKpYIE7ZD/f/ fuVA== X-Gm-Message-State: AOAM532kCl28qZRJEOY2EzFM2w0Jfv9s/5SuxCt8q1rxhEvkXsqqveAs d5W7QcD2coyntznU+jQPppK0QOUi9RlKeCiKmO8= X-Google-Smtp-Source: ABdhPJy6Hg+rsTi1P6bo6wi7EKEqiwOO7Rb2mBxRJDCxdvZywLSUQAaS33Vao9Z7pxmRUnNi1vgVo8GSBPCu+3i9Gyg= X-Received: by 2002:a1f:5682:: with SMTP id k124mr1995507vkb.20.1617805764137; Wed, 07 Apr 2021 07:29:24 -0700 (PDT) MIME-Version: 1.0 References: <1616868399-82848-1-git-send-email-guoren@kernel.org> <1616868399-82848-4-git-send-email-guoren@kernel.org> <20210407094224.GA3393992@infradead.org> In-Reply-To: <20210407094224.GA3393992@infradead.org> From: =?UTF-8?Q?Christoph_M=C3=BCllner?= Date: Wed, 7 Apr 2021 16:29:12 +0200 Message-ID: Subject: Re: [PATCH v4 3/4] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 To: Christoph Hellwig Cc: Peter Zijlstra , Guo Ren , linux-riscv , Linux Kernel Mailing List , linux-csky@vger.kernel.org, linux-arch , Guo Ren , Will Deacon , Ingo Molnar , Waiman Long , Arnd Bergmann , Anup Patel X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210407_152926_314031_F2F3DBC3 X-CRM114-Status: GOOD ( 21.01 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Apr 7, 2021 at 11:43 AM Christoph Hellwig wrote: > > On Tue, Apr 06, 2021 at 09:15:50AM +0200, Peter Zijlstra wrote: > > Anyway, given you have such a crap architecture (and here I thought > > RISC-V was supposed to be a modern design *sigh*), you had better go > > look at the sparc64 atomic implementation which has a software backoff > > for failed CAS in order to make fwd progress. > > It wasn't supposed to be modern. It was supposed to use boring old > ideas. Where it actually did that it is a great ISA, in parts where > academics actually tried to come up with cool or state of the art > ideas (interrupt handling, tlb shootdowns, the totally fucked up > memory model) it turned into a trainwreck. Gentlemen, please rethink your wording. RISC-V is neither "crap" nor a "trainwreck", regardless if you like it or not. The comparison with sparc64 is not applicable, as sparc64 does not have LL/SC instructions. Further, it is not the case that RISC-V has no guarantees at all. It just does not provide a forward progress guarantee for a synchronization implementation, that writes in an endless loop to a memory location while trying to complete an LL/SC loop on the same memory location at the same time. If there's a reasonable algorithm, that relies on forward progress in this case, then we should indeed think about that, but I haven't seen one so far. The whole MCF lock idea is to actually spin on different memory locations per CPU to improve scalability (reduce cacheline bouncing). That's a clear indicator, that well-scaling synchronization algorithms need to avoid contended cache lines anyways. RISC-V defines LR/SC loops consisting of up to 16 instructions as constrained LR/SC loops. Such constrained LR/SC loops provide the required forward guarantees, that are expected (similar to what other architectures, like AArch64, have). What RISC-V does not have is sub-word atomics and if required, we would have to implement them as LL/SC sequences. And yes, using atomic instructions is preferred over using LL/SC, because atomics will tend to perform better (less instructions and less spilled registers). But that actually depends on the actual ISA implementation. Respectfully, Christoph _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv