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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=nSPxA9X500mgbh9IFPNCBvtp5v+qregrP1EhmFh9wNQ=; b=W3IemAMpC7liSIMx0Fh0cqE8v+fE1oXtaAlW9j2P8A+exKRSzf6PWReOxDXMRZl7tA ePAnJIMj1dApZJ5EIwz3Uatax0Y2DkqjW2M7Ri6fqJE1BmXf+s5dX95sMmnrdrjcr07h olw955e1z9ffLUWtEjJ4RQSQzpIxfIm69S9IlFGDtetQuPFaJVHkai2UjpP1wEYN4M2c hLIk9VE5uBhRB16ZREvqDdMYMN2UsijZ8YevRZoqqq433CK5igheOAfCjGaKx3gm5+dD D+MPlN6nTOHYwTTH/PqeyCvJYspE3F00ogJu9HAe1qRqDaJl2R1m74MJxWcpZzMew6ra v3iQ== X-Gm-Message-State: ANhLgQ1RqKngnkI/KWfO1WtDOl8MvTjh+9m+ERE2qYYioo222g7F56iV 28XMhC/kJztcVOvbmwqhAr5nISLTIu+IoYDKdzbw8g308v0= X-Google-Smtp-Source: ADFU+vtMECKg0iE77xyeveafTTIJe1NctM9ZS1gbqJZXUfdRwOkJDNRqliHHiYwApvHERLRaNfSDyKeu+F6P0l3jIE0= X-Received: by 2002:a37:a8d8:: with SMTP id r207mr18024852qke.123.1583830471137; Tue, 10 Mar 2020 01:54:31 -0700 (PDT) MIME-Version: 1.0 References: <20200308094954.13258-1-guoren@kernel.org> <95e3bba4-65c0-8991-9523-c16977f6350f@c-sky.com> In-Reply-To: <95e3bba4-65c0-8991-9523-c16977f6350f@c-sky.com> From: Greentime Hu Date: Tue, 10 Mar 2020 16:54:19 +0800 Message-ID: Subject: Re: [RFC PATCH V3 00/11] riscv: Add vector ISA support To: LIU Zhiwei Content-Type: text/plain; charset="UTF-8" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200310_015432_966534_583794B3 X-CRM114-Status: GOOD ( 14.74 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, Guo Ren , arnd@arndb.de, Anup.Patel@wdc.com, Linux Kernel Mailing List , linux-csky@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , guoren@kernel.org, linux-riscv , Dave Martin Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Mar 9, 2020 at 6:27 PM LIU Zhiwei wrote: > On 2020/3/9 11:41, Greentime Hu wrote: > > On Sun, Mar 8, 2020 at 5:50 PM wrote: > >> From: Guo Ren > >> > >> The implementation follow the RISC-V "V" Vector Extension draft v0.8 with > >> 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1]. > >> > >> The patch implement basic context switch, sigcontext save/restore and > >> ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen > >> is implemented. We need to discuss about vlen-size for libc sigcontext and > >> ptrace (the maximum size of vlen is unlimited in spec). > >> > >> Puzzle: > >> Dave Martin has talked "Growing CPU register state without breaking ABI" [2] > >> before, and riscv also met vlen size problem. Let's discuss the common issue > >> for all architectures and we need a better solution for unlimited vlen. > >> > >> Any help are welcomed :) > >> > >> 1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3 > > Hi Guo, > > > > Thanks for your patch. > > It seems the qemu repo doesn't have this branch? > Hi Greentime, > > It's a promise from me. Now it's ready. You can turn on vector by > "qemu-system-riscv64 -cpu rv64,v=true,vext_spec=v0.7.1". > > Zhiwei > > Hi Zhiwei, Thank you, I see the branch in the repo now. I will give it a try and let you know if I have any problem. :)