From: Greentime Hu <greentime.hu@sifive.com>
To: Rob Herring <robh@kernel.org>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
hes@sifive.com, Erik Danie <erik.danie@sifive.com>,
Zong Li <zong.li@sifive.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Michael Turquette <mturquette@baylibre.com>,
sboyd@kernel.org, lorenzo.pieralisi@arm.com,
Philipp Zabel <p.zabel@pengutronix.de>,
alex.dewar90@gmail.com, khilman@baylibre.com,
hayashi.kunihiko@socionext.com, vidyas@nvidia.com,
jh80.chung@samsung.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org,
linux-riscv <linux-riscv@lists.infradead.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-clk@vger.kernel.org, Bjorn Helgaas <helgaas@kernel.org>
Subject: Re: [PATCH v2 4/6] dt-bindings: PCI: Add SiFive FU740 PCIe host controller
Date: Mon, 29 Mar 2021 11:39:54 +0800 [thread overview]
Message-ID: <CAHCEehKw2Sb6DN-hQCZB8-ARuaOf47mmzS18Fqm1amr4sXVCRg@mail.gmail.com> (raw)
In-Reply-To: <20210323203508.GA1251968@robh.at.kernel.org>
Rob Herring <robh@kernel.org> 於 2021年3月24日 週三 上午4:35寫道：
>
> On Thu, Mar 18, 2021 at 02:08:11PM +0800, Greentime Hu wrote:
> > Add PCIe host controller DT bindings of SiFive FU740.
> >
> > Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> > ---
> > .../bindings/pci/sifive,fu740-pcie.yaml | 119 ++++++++++++++++++
> > 1 file changed, 119 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml
[...]
> > +examples:
> > + - |
> > + pcie@e00000000 {
> > + #address-cells = <3>;
> > + #interrupt-cells = <1>;
> > + #size-cells = <2>;
> > + compatible = "sifive,fu740-pcie";
> > + reg = <0xe 0x00000000 0x1 0x0
>
> Humm, 4GB for DBI space? The DWC controller doesn't have that much
> space, and the kernel will map *all* of that. That's not an
> insignificant amount of memory just for page tables.
Thank you for review and point this out. :)
I check the spec description for DBI in DWC_pcie_ctl_dm_databook.pdf
section 3.15 3.16 and table 3-17.
I think CX_SRIOV_ENABLE and CX_ARI_ENABLE will be set to 0 because
these 2 are endpoint mode features.
Single Root I/O Virtualization (SR-IOV) This section describes the
SR-IOV features implemented in EP mode. The parameter for enabling
SR-IOV is CX_SRIOV_ENABLE
Alternative Routing-ID Interpretation (ARI) ARI allows an endpoint to
support more than eight physical functions (PFs). ARI is enabled by
the CX_ARI_ENABLE parameter.
So based on Table 3-17, we will need to map 2GB(bit30) instead of 4GB(bit31).
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next prev parent reply other threads:[~2021-03-29 18:54 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-18 6:08 [PATCH v2 0/6] Add SiFive FU740 PCIe host controller driver support Greentime Hu
2021-03-18 6:08 ` [PATCH v2 1/6] clk: sifive: Add pcie_aux clock in prci driver for PCIe driver Greentime Hu
2021-03-18 6:08 ` [PATCH v2 2/6] clk: sifive: Use reset-simple " Greentime Hu
2021-03-29 19:14 ` Stephen Boyd
2021-03-30 3:36 ` Greentime Hu
2021-03-31 0:24 ` Palmer Dabbelt
2021-03-18 6:08 ` [PATCH v2 3/6] MAINTAINERS: Add maintainers for SiFive FU740 " Greentime Hu
2021-03-18 6:08 ` [PATCH v2 4/6] dt-bindings: PCI: Add SiFive FU740 PCIe host controller Greentime Hu
2021-03-19 3:56 ` Krzysztof Wilczyński
2021-03-19 21:49 ` Rob Herring
2021-03-23 20:35 ` Rob Herring
2021-03-29 3:39 ` Greentime Hu [this message]
2021-03-18 6:08 ` [PATCH v2 5/6] PCI: fu740: Add SiFive FU740 PCIe host controller driver Greentime Hu
2021-03-19 4:37 ` Krzysztof Wilczyński
2021-03-19 4:42 ` Krzysztof Wilczyński
2021-03-18 6:08 ` [PATCH v2 6/6] riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC Greentime Hu
2021-03-31 0:24 ` Palmer Dabbelt
2021-04-19 2:43 ` Greentime Hu
2021-04-19 2:48 ` Greentime Hu
2021-03-29 19:12 ` [PATCH v2 0/6] Add SiFive FU740 PCIe host controller driver support Stephen Boyd
2021-04-01 6:16 ` Greentime Hu
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