From: Greentime Hu <greentime.hu@sifive.com>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>
Cc: linux-arch@vger.kernel.org, Guo Ren <guoren@linux.alibaba.com>,
arnd@arndb.de, Anup.Patel@wdc.com,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-csky@vger.kernel.org, Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
guoren@kernel.org, linux-riscv <linux-riscv@lists.infradead.org>,
Dave Martin <Dave.Martin@arm.com>
Subject: Re: [RFC PATCH V3 00/11] riscv: Add vector ISA support
Date: Tue, 10 Mar 2020 17:19:36 +0800 [thread overview]
Message-ID: <CAHCEehLq5f+DGusL0T4ZUuJ2hTRhSyLSGRpKHhq5b4J3nXfBHg@mail.gmail.com> (raw)
In-Reply-To: <CAHCEehK0rgBpEzrWar1UTWJoOz=OQi18iw4Y+v3z5Hi=7JCEWw@mail.gmail.com>
On Tue, Mar 10, 2020 at 4:54 PM Greentime Hu <greentime.hu@sifive.com> wrote:
>
> On Mon, Mar 9, 2020 at 6:27 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
> > On 2020/3/9 11:41, Greentime Hu wrote:
> > > On Sun, Mar 8, 2020 at 5:50 PM <guoren@kernel.org> wrote:
> > >> From: Guo Ren <guoren@linux.alibaba.com>
> > >>
> > >> The implementation follow the RISC-V "V" Vector Extension draft v0.8 with
> > >> 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1].
> > >>
> > >> The patch implement basic context switch, sigcontext save/restore and
> > >> ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen
> > >> is implemented. We need to discuss about vlen-size for libc sigcontext and
> > >> ptrace (the maximum size of vlen is unlimited in spec).
> > >>
> > >> Puzzle:
> > >> Dave Martin has talked "Growing CPU register state without breaking ABI" [2]
> > >> before, and riscv also met vlen size problem. Let's discuss the common issue
> > >> for all architectures and we need a better solution for unlimited vlen.
> > >>
> > >> Any help are welcomed :)
> > >>
> > >> 1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3
> > > Hi Guo,
> > >
> > > Thanks for your patch.
> > > It seems the qemu repo doesn't have this branch?
> > Hi Greentime,
> >
> > It's a promise from me. Now it's ready. You can turn on vector by
> > "qemu-system-riscv64 -cpu rv64,v=true,vext_spec=v0.7.1".
> >
> > Zhiwei
> >
> >
>
> Hi Zhiwei,
>
> Thank you, I see the branch in the repo now. I will give it a try and
> let you know if I have any problem. :)
Hi Zhiwei & Guo,
It seems current version only support v0.7.1 in qemu but this patchset
is verified in qemu too and it is based on 0.8.
Would you please provide the qemu with 0.8 vector spec supported? or
Did I miss something?
489 if (cpu->cfg.vext_spec) {
490 if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
491 vext_version = VEXT_VERSION_0_07_1;
492 } else {
493 error_setg(errp,
494 "Unsupported vector spec version '%s'",
495 cpu->cfg.vext_spec);
496 return;
497 }
498 }
By the way, can I specify vlen in Qemu?
Thank you. :)
next prev parent reply other threads:[~2020-03-10 9:19 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-08 9:49 [RFC PATCH V3 00/11] riscv: Add vector ISA support guoren
2020-03-08 9:49 ` [RFC PATCH V3 01/11] riscv: Separate patch for cflags and aflags guoren
2020-03-08 9:49 ` [RFC PATCH V3 02/11] riscv: Rename __switch_to_aux -> fpu guoren
2020-03-08 9:49 ` [RFC PATCH V3 03/11] riscv: Extending cpufeature.c to detect V-extension guoren
2020-03-08 9:49 ` [RFC PATCH V3 04/11] riscv: Add CSR defines related to VECTOR extension guoren
2020-03-08 9:49 ` [RFC PATCH V3 05/11] riscv: Add vector feature to compile guoren
2020-03-08 9:49 ` [RFC PATCH V3 06/11] riscv: Add has_vector detect guoren
2020-03-08 9:49 ` [RFC PATCH V3 07/11] riscv: Reset vector register guoren
2020-03-08 9:49 ` [RFC PATCH V3 08/11] riscv: Add vector struct and assembler definitions guoren
2020-03-08 9:49 ` [RFC PATCH V3 09/11] riscv: Add task switch support for VECTOR guoren
2020-03-08 9:49 ` [RFC PATCH V3 10/11] riscv: Add ptrace support guoren
2020-03-08 9:49 ` [RFC PATCH V3 11/11] riscv: Add sigcontext save/restore guoren
2020-03-09 3:41 ` [RFC PATCH V3 00/11] riscv: Add vector ISA support Greentime Hu
2020-03-09 10:27 ` LIU Zhiwei
2020-03-10 8:54 ` Greentime Hu
2020-03-10 9:19 ` Greentime Hu [this message]
2020-03-12 3:14 ` LIU Zhiwei
2020-03-23 4:00 ` Greentime Hu
2020-03-24 3:41 ` Guo Ren
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