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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=AEususRD/p1RLs1UC0IHIQOxqNXf3vrCgl3jM8yPylM=; b=IT4a0mZOkwHw/2IV5sAG7zKRUrLTCiMYA+/qm8uDjGFA9YkEOw67nm9W6/6x+Fmp+d OMRmYaIazED5nkCJEFuEDTTXZyE9noobavY7k7Ab4eUF9iZwp5oO+gydsO4C4OFHgpwD RpDEld59JbrHbT/qCWx2nRyT2MRcAfdH8d+uKnQSFDxFuGtJ0880HTirYtQ5fSd/9niE 9PL06xyXyOmYkjlrR8IfdvJdRPODci2YQVO6CliqmcyqrmFdYey16YqIJeWK7qJ4H5Fn xsMsGvxkfvZAxrCZaggkVk6Uv4MBndCGQdoYWrzZv8msTs8J5mQMcMO10T9b+JFXvxZm VncA== X-Gm-Message-State: APjAAAUMEOOS02J5OS2Ms2OZzWYLMoorhhDKw7p0WZUCydEQpKNsN02R pyEKIPDqttJUj5CkQoWHymt8akn3J5XCcHpgYzg4lg== X-Google-Smtp-Source: APXvYqz1GXfTgzlkZFJTZ7cQNct2UId8Tmq9X/mNPWaQHmPrJUI6MVbVOZbWegp1Us89EVl8iOBnaJ2+PEhtxHG/Tg4= X-Received: by 2002:a2e:9f0f:: with SMTP id u15mr14579422ljk.54.1566281024086; Mon, 19 Aug 2019 23:03:44 -0700 (PDT) MIME-Version: 1.0 References: <20190818082935.14869-1-hch@lst.de> <20190819060904.GA4841@zn.tnic> <20190819062619.GA20211@lst.de> In-Reply-To: <20190819062619.GA20211@lst.de> From: Yash Shah Date: Tue, 20 Aug 2019 11:33:07 +0530 Message-ID: Subject: Re: [PATCH] riscv: move sifive_l2_cache.c to drivers/soc To: Christoph Hellwig X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190819_230348_148218_959BC052 X-CRM114-Status: GOOD ( 14.83 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Palmer Dabbelt , "linux-kernel@vger.kernel.org List" , Borislav Petkov , Paul Walmsley , linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Aug 19, 2019 at 11:56 AM Christoph Hellwig wrote: > > On Mon, Aug 19, 2019 at 08:09:04AM +0200, Borislav Petkov wrote: > > On Sun, Aug 18, 2019 at 10:29:35AM +0200, Christoph Hellwig wrote: > > > The sifive_l2_cache.c is in no way related to RISC-V architecture > > > memory management. It is a little stub driver working around the fact > > > that the EDAC maintainers prefer their drivers to be structured in a > > > certain way > > > > That changed recently so I guess we can do the per-IP block driver after > > all, if people would still prefer it. > > That would seem like the best idea. But I don't really know this code > well enough myself, and I really need to get this code out of the > forced on RISC-V codebase as some SOCs I'm working with simply don't > have the memory for it.. > > So unless someone signs up to do a per-IP block edac drivers instead > very quickly I'd still like to see something like this go into 5.4 > for now. As of now, we can pull this patch into 5.4. Later, I will review if per-IP block edac driver is needed and if so, will take care of implementing it. - Yash _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv