From: Yash Shah <yash.shah@sifive.com>
To: linux-edac@vger.kernel.org, linux-riscv@lists.infradead.org,
Palmer Dabbelt <palmer@sifive.com>,
Borislav Petkov <bp@alien8.de>, James Morse <james.morse@arm.com>
Cc: aou@eecs.berkeley.edu, paulmck@linux.ibm.com,
gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org,
nicolas.ferre@microchip.com,
Sachin Ghadi <sachin.ghadi@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
mchehab@kernel.org, davem@davemloft.net
Subject: Re: [PATCH v2] edac: sifive: Add EDAC platform driver for SiFive SoCs
Date: Tue, 21 May 2019 11:00:59 +0530 [thread overview]
Message-ID: <CAJ2_jOG9Ag0spbh3YCxavUE5XEAUP1pHcgCZ56Nu2u4TqfrzHQ@mail.gmail.com> (raw)
In-Reply-To: <1557142026-15949-2-git-send-email-yash.shah@sifive.com>
On Mon, May 6, 2019 at 4:57 PM Yash Shah <yash.shah@sifive.com> wrote:
>
> The initial ver of EDAC driver supports:
> - ECC event monitoring and reporting through the EDAC framework for SiFive
> L2 cache controller.
>
> The EDAC driver registers for notifier events from the L2 cache controller
> driver (arch/riscv/mm/sifive_l2_cache.c) for L2 ECC events
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> Reviewed-by: James Morse <james.morse@arm.com>
> ---
> This patch depends on patch
> 'RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs'
> https://lkml.org/lkml/2019/5/6/255
The prerequisite patch (sifive_l2_cache driver) has been merged into
mainline v5.2-rc1
It should be OK to merge this edac driver now.
- Yash
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next prev parent reply other threads:[~2019-05-21 5:31 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-06 11:27 [PATCH v2] EDAC support for SiFive SoCs Yash Shah
2019-05-06 11:27 ` [PATCH v2] edac: sifive: Add EDAC platform driver " Yash Shah
2019-05-21 5:30 ` Yash Shah [this message]
2019-05-21 18:21 ` Borislav Petkov
2019-05-22 9:13 ` James Morse
2019-05-22 9:34 ` Boris Petkov
2019-06-07 6:43 ` Borislav Petkov
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