From: Guo Ren <guoren@kernel.org>
To: Christoph Hellwig <hch@lst.de>
Cc: Anup Patel <anup.patel@wdc.com>,
Palmer Dabbelt <palmerdabbelt@google.com>,
Arnd Bergmann <arnd@arndb.de>,
linux-riscv <linux-riscv@lists.infradead.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-arch <linux-arch@vger.kernel.org>,
Guo Ren <guoren@linux.alibaba.com>
Subject: Re: [PATCH V5 2/3] riscv: Add ASID-based tlbflushing methods
Date: Mon, 31 May 2021 20:20:32 +0800 [thread overview]
Message-ID: <CAJF2gTQ3pG-EoDnqonEcMyKzdXPkf5s7qcyLSm9x79RiETCWkg@mail.gmail.com> (raw)
In-Reply-To: <20210531061742.GB824@lst.de>
On Mon, May 31, 2021 at 2:17 PM Christoph Hellwig <hch@lst.de> wrote:
>
> On Sun, May 30, 2021 at 04:49:25PM +0000, guoren@kernel.org wrote:
> > From: Guo Ren <guoren@linux.alibaba.com>
> >
> > Implement optimized version of the tlb flushing routines for systems
> > using ASIDs. These are behind the use_asid_allocator static branch to
> > not affect existing systems not using ASIDs.
>
> I still think the code duplication and exposing of new code in a global
> header here is a bad idea and would suggest the version I sent instead.
Your idea is in the third patch, and I also add you with
Co-developed-by. Please have a look:
https://lore.kernel.org/linux-riscv/1622393366-46079-4-git-send-email-guoren@kernel.org/T/#u
[PATCH V5 3/3] riscv: tlbflush: Optimize coding convention
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
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next prev parent reply other threads:[~2021-05-31 12:20 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-30 16:49 [PATCH V5 0/3] riscv: Fixup asid_allocator remaining issues guoren
2021-05-30 16:49 ` [PATCH V5 1/3] riscv: Use global mappings for kernel pages guoren
2021-05-30 16:49 ` [PATCH V5 2/3] riscv: Add ASID-based tlbflushing methods guoren
2021-05-31 6:17 ` Christoph Hellwig
2021-05-31 12:20 ` Guo Ren [this message]
2021-05-30 16:49 ` [PATCH V5 3/3] riscv: tlbflush: Optimize coding convention guoren
2021-06-06 9:03 [RFC PATCH v2 00/11] riscv: Add DMA_COHERENT support for Allwinner D1 guoren
2021-06-06 9:03 ` [PATCH V5 2/3] riscv: Add ASID-based tlbflushing methods guoren
2021-06-06 14:38 ` Christoph Hellwig
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