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Fri, 28 Oct 2022 21:25:14 -0700 (PDT) X-Gm-Message-State: ACrzQf21qfpzj00CpweMgvTn11UDDN7eaiNlG8hu2eysQrop/s5WCoa5 EZwNEBjygCsBgICFJL2w2Lf4iyh7CU6SyHty4BU= X-Google-Smtp-Source: AMsMyM4U+XLGWneF25rSvG0PdhbqMRiauzCcUyYwLQozxUxetPJGDoBdTR7JO/wJ2kk58GWp0y2oWsZihOLcyTvwVg4= X-Received: by 2002:a4a:2144:0:b0:481:a4:d2b0 with SMTP id u65-20020a4a2144000000b0048100a4d2b0mr1153471oou.48.1667017514013; Fri, 28 Oct 2022 21:25:14 -0700 (PDT) MIME-Version: 1.0 References: <20221028165921.94487-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221028165921.94487-5-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20221028165921.94487-5-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Guo Ren Date: Sat, 29 Oct 2022 12:25:01 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC To: Prabhakar Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Conor Dooley , Anup Patel , Atish Patra , Heinrich Schuchardt , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das , Lad Prabhakar X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221028_212516_866094_AB63D663 X-CRM114-Status: GOOD ( 23.68 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Sat, Oct 29, 2022 at 12:59 AM Prabhakar wrote: > > From: Lad Prabhakar > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP > Single). > > RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we > will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's. > r9a07g043f.dtsi includes RZ/Five SoC specific blocks. > > Below are the RZ/Five SoC specific blocks added in the initial DTSI which > can be used to boot via initramfs on RZ/Five SMARC EVK: > - AX45MP CPU > - PLIC > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi > > Signed-off-by: Lad Prabhakar > --- > v4 -> v5 > * Fixed riscv,ndev value (should be 511) > * Reworked completely (sort of new patch) > > v3 -> v4 > * No change > > v2 -> v3 > * Fixed clock entry for CPU core > * Fixed timebase frequency to 12MHz > * Fixed sorting of the nodes > * Included RB tags > > v1 -> v2 > * Dropped including makefile change > * Updated ndev count > --- > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++ > 1 file changed, 57 insertions(+) > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > new file mode 100644 > index 000000000000..50134be548f5 > --- /dev/null > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > @@ -0,0 +1,57 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +/* > + * Device Tree Source for the RZ/Five SoC > + * > + * Copyright (C) 2022 Renesas Electronics Corp. > + */ > + > +#include > + > +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32) > + > +#include The initial patch shouldn't be broken. Combine them together with the minimal components and add others late. Don't separate the DTS files. > + > +/ { > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + timebase-frequency = <12000000>; > + > + cpu0: cpu@0 { > + compatible = "andestech,ax45mp", "riscv"; > + device_type = "cpu"; > + reg = <0x0>; > + status = "okay"; > + riscv,isa = "rv64imafdc"; > + mmu-type = "riscv,sv39"; > + i-cache-size = <0x8000>; > + i-cache-line-size = <0x40>; > + d-cache-size = <0x8000>; > + d-cache-line-size = <0x40>; > + clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; > + > + cpu0_intc: interrupt-controller { > + #interrupt-cells = <1>; > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + }; > + }; > + }; > +}; > + > +&soc { > + interrupt-parent = <&plic>; > + > + plic: interrupt-controller@12c00000 { > + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100"; > + #interrupt-cells = <2>; > + #address-cells = <0>; > + riscv,ndev = <511>; > + interrupt-controller; > + reg = <0x0 0x12c00000 0 0x400000>; > + clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; > + power-domains = <&cpg>; > + resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; Ditto, Where is cpg? in r9a07g043.dtsi? > + interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>; > + }; > +}; > -- > 2.25.1 > -- Best Regards Guo Ren _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv