From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C717C4338F for ; Tue, 17 Aug 2021 06:29:37 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BEA8660C3F for ; Tue, 17 Aug 2021 06:29:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org BEA8660C3F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ZXNJ1ZemAHM23QT8WB7s1CwuFDSW0FD8ZZSBHKEx/KA=; b=sYTJH7yShR7BQf LXsoBUOLcAx3lrMUjHjClxlP49AjTJeD5a3rNf5YjGtr4uX9moybOIc6OEfHSmPcZr64bjrGqdfkq ctWkOtykkjUUDbfJ5dvNcFl6ZDnAJ6BWh6WEC0E8WZ1dn/rXVDg5CDVJewEQ6jcNoekQPC0bm9HzV DXgtkcQU9d2ub+EKr9ALUwhPcQzsMuA40lzr/hwSYTCz6t6qxYviQvz7/VaEfKI7Du94Nf/O7Gqep ECffYU/tfv5KUm2dhoozVmNexz657AQZG2kNS+461oiOR5B5fCcr/idKV5s6ko4ya0ebNtADWnwNR LPcdEYjGP9VEeqjVxLnA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mFsas-001FHP-0Q; Tue, 17 Aug 2021 06:29:02 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mFsam-001FGh-Ea for linux-riscv@lists.infradead.org; Tue, 17 Aug 2021 06:29:00 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 41D6A61042 for ; Tue, 17 Aug 2021 06:28:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1629181735; bh=y0HUvMC1sQq6AFsYEi1z1jFYlX4llWlauvdgseAQwKA=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=J1KVWpnFU1z0mvqeX2LN1w6g64cU1amSanSKTQjm3RQexMOGjK8xrAa4oM+84elK3 wD5DClu7WoAMOZVwubL1IkCEvIC/6wFdnhliYeQxQ7Q2fzv0FJHcYc0y6ZyTg8Qdut Jjm22sRwOpBt0cIl1j7GKOBTNSYE4q4HJZk1W+wzwbPy2/bt3zbB3NnB7KTMdV9sGr 8zrtZ82M+maNuYd+VQMwSb/tnbt44R+yZgyy+T0KjGL9KUK4lyKhFD+vLCeFJ/250G VNgPFyB0N9KG0j4MLl6HO93iW//JJqOF34ENH3HMkAoWMX+6EZvJLJ/LpiQ32bUmdN Q9FlNiUkXXTpA== Received: by mail-lj1-f173.google.com with SMTP id y6so14428998lje.2 for ; Mon, 16 Aug 2021 23:28:55 -0700 (PDT) X-Gm-Message-State: AOAM533G1sfxq2aKbohHlTfmtB3UnnRZNQw+OLzia8wfT+TPQpeZtkxb 5DxljgkaKF7aeLpxeOPegNBuW4V5hhvtRv4gSck= X-Google-Smtp-Source: ABdhPJwyPyxj47GyA0nsFM2W/NJJj+2fT6rvJAeElZihgyXsd/VEqIv7awRZVKSaYuNO+nnX2aL5/VPBehBQGurYRZc= X-Received: by 2002:a05:651c:39c:: with SMTP id e28mr1728053ljp.498.1629181733447; Mon, 16 Aug 2021 23:28:53 -0700 (PDT) MIME-Version: 1.0 References: <20210723214031.3251801-1-atish.patra@wdc.com> <20210723214031.3251801-2-atish.patra@wdc.com> In-Reply-To: From: Guo Ren Date: Tue, 17 Aug 2021 14:28:42 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RFC 1/5] RISC-V: Implement arch_sync_dma* functions To: Atish Patra Cc: Atish Patra , devicetree , Albert Ou , Guo Ren , Frank Rowand , Linux Kernel Mailing List , Christoph Hellwig , iommu@lists.linux-foundation.org, Rob Herring , Palmer Dabbelt , Paul Walmsley , Tobias Klauser , Robin Murphy , linux-riscv , Dmitry Vyukov X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210816_232856_571122_8FC45AD8 X-CRM114-Status: GOOD ( 35.19 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Aug 17, 2021 at 11:24 AM Atish Patra wrote: > > On Mon, Aug 16, 2021 at 6:48 PM Guo Ren wrote: > > > > On Sat, Jul 24, 2021 at 5:40 AM Atish Patra wrote: > > > > > > To facilitate streaming DMA APIs, this patch introduces a set of generic > > > cache operations related dma sync. Any platform can use the generic ops > > > to provide platform specific cache management operations. Once the > > > standard RISC-V CMO extension is available, it can be built on top of it. > > > > > > Signed-off-by: Atish Patra > > > --- > > > arch/riscv/include/asm/dma-noncoherent.h | 19 +++++++ > > > arch/riscv/mm/Makefile | 1 + > > > arch/riscv/mm/dma-noncoherent.c | 66 ++++++++++++++++++++++++ > > > 3 files changed, 86 insertions(+) > > > create mode 100644 arch/riscv/include/asm/dma-noncoherent.h > > > create mode 100644 arch/riscv/mm/dma-noncoherent.c > > > > > > diff --git a/arch/riscv/include/asm/dma-noncoherent.h b/arch/riscv/include/asm/dma-noncoherent.h > > > new file mode 100644 > > > index 000000000000..5bdb03c9c427 > > > --- /dev/null > > > +++ b/arch/riscv/include/asm/dma-noncoherent.h > > > @@ -0,0 +1,19 @@ > > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > > +/* > > > + * Copyright (c) 2021 Western Digital Corporation or its affiliates. > > > + */ > > > + > > > +#ifndef __ASM_RISCV_DMA_NON_COHERENT_H > > > +#define __ASM_RISCV_DMA_NON_COHERENT_H > > > + > > > +#ifdef CONFIG_RISCV_DMA_NONCOHERENT > > > +struct riscv_dma_cache_sync { > > > + void (*cache_invalidate)(phys_addr_t paddr, size_t size); > > > + void (*cache_clean)(phys_addr_t paddr, size_t size); > > > + void (*cache_flush)(phys_addr_t paddr, size_t size); > > > +}; > > I like the style like this than my previous patch which using > > sbi_call. The c906 has custom instructions that could be called in > > S-mode directly. > > > > How are you going to include the custom instructions in the upstream kernel ? In errata, call set_ops? I'm headache with that issue. > > > Hope the patch could be soon merged, after correct the > > DMA_FROM/TO_DEVICE/BIDIRECTIONAL and alternatives ops_set. > > > > > + > > > +void riscv_dma_cache_sync_set(struct riscv_dma_cache_sync *ops); > > > +#endif > > > + > > > +#endif > > > diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile > > > index 7ebaef10ea1b..959bef49098b 100644 > > > --- a/arch/riscv/mm/Makefile > > > +++ b/arch/riscv/mm/Makefile > > > @@ -27,3 +27,4 @@ KASAN_SANITIZE_init.o := n > > > endif > > > > > > obj-$(CONFIG_DEBUG_VIRTUAL) += physaddr.o > > > +obj-$(CONFIG_RISCV_DMA_NONCOHERENT) += dma-noncoherent.o > > > diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c > > > new file mode 100644 > > > index 000000000000..2f6e9627c4aa > > > --- /dev/null > > > +++ b/arch/riscv/mm/dma-noncoherent.c > > > @@ -0,0 +1,66 @@ > > > +// SPDX-License-Identifier: GPL-2.0-only > > > +/* > > > + * RISC-V specific functions to support DMA for non-coherent devices > > > + * > > > + * Copyright (c) 2021 Western Digital Corporation or its affiliates. > > > + */ > > > + > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > + > > > +static struct riscv_dma_cache_sync *dma_cache_sync; > > > +unsigned long riscv_dma_uc_offset; > > > + > > > +static void __dma_sync(phys_addr_t paddr, size_t size, enum dma_data_direction dir) > > > +{ > > > + if ((dir == DMA_FROM_DEVICE) && (dma_cache_sync->cache_invalidate)) > > > + dma_cache_sync->cache_invalidate(paddr, size); > > > + else if ((dir == DMA_TO_DEVICE) && (dma_cache_sync->cache_clean)) > > > + dma_cache_sync->cache_clean(paddr, size); > > > + else if ((dir == DMA_BIDIRECTIONAL) && dma_cache_sync->cache_flush) > > > + dma_cache_sync->cache_flush(paddr, size); > > > +} > > > + > > > +void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, enum dma_data_direction dir) > > > +{ > > > + if (!dma_cache_sync) > > > + return; > > > + > > > + __dma_sync(paddr, size, dir); > > > +} > > > + > > > +void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, enum dma_data_direction dir) > > > +{ > > > + if (!dma_cache_sync) > > > + return; > > > + > > > + __dma_sync(paddr, size, dir); > > > +} > > > + > > > +void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, > > > + const struct iommu_ops *iommu, bool coherent) > > > +{ > > > + /* If a specific device is dma-coherent, set it here */ > > > + dev->dma_coherent = coherent; > > > +} > > > + > > > +void arch_dma_prep_coherent(struct page *page, size_t size) > > > +{ > > > + void *flush_addr = page_address(page); > > > + > > > + memset(flush_addr, 0, size); > > > + if (dma_cache_sync && dma_cache_sync->cache_flush) > > > + dma_cache_sync->cache_flush(__pa(flush_addr), size); > > > +} > > > + > > > +void riscv_dma_cache_sync_set(struct riscv_dma_cache_sync *ops) > > > +{ > > > + dma_cache_sync = ops; > > > +} > > > -- > > > 2.31.1 > > > > > > _______________________________________________ > > > iommu mailing list > > > iommu@lists.linux-foundation.org > > > https://lists.linuxfoundation.org/mailman/listinfo/iommu > > > > > > > > -- > > Best Regards > > Guo Ren > > > > ML: https://lore.kernel.org/linux-csky/ > > _______________________________________________ > > iommu mailing list > > iommu@lists.linux-foundation.org > > https://lists.linuxfoundation.org/mailman/listinfo/iommu > > > > -- > Regards, > Atish -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv