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Mon, 05 Apr 2021 09:46:09 -0700 (PDT) MIME-Version: 1.0 References: <1616868399-82848-1-git-send-email-guoren@kernel.org> <1616868399-82848-4-git-send-email-guoren@kernel.org> <4d0dbaa0-1f96-470c-0ed0-04f6827ea384@redhat.com> In-Reply-To: <4d0dbaa0-1f96-470c-0ed0-04f6827ea384@redhat.com> From: Guo Ren Date: Tue, 6 Apr 2021 00:45:58 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 3/4] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 To: Waiman Long Cc: Peter Zijlstra , linux-riscv , Linux Kernel Mailing List , linux-csky@vger.kernel.org, linux-arch , Guo Ren , Will Deacon , Ingo Molnar , Arnd Bergmann , Anup Patel X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210405_174614_338587_E74323A9 X-CRM114-Status: GOOD ( 26.56 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Mar 30, 2021 at 10:09 PM Waiman Long wrote: > > On 3/29/21 11:13 PM, Guo Ren wrote: > > On Mon, Mar 29, 2021 at 8:50 PM Peter Zijlstra wrote: > >> On Mon, Mar 29, 2021 at 08:01:41PM +0800, Guo Ren wrote: > >>> u32 a = 0x55aa66bb; > >>> u16 *ptr = &a; > >>> > >>> CPU0 CPU1 > >>> ========= ========= > >>> xchg16(ptr, new) while(1) > >>> WRITE_ONCE(*(ptr + 1), x); > >>> > >>> When we use lr.w/sc.w implement xchg16, it'll cause CPU0 deadlock. > >> Then I think your LL/SC is broken. > >> > >> That also means you really don't want to build super complex locking > >> primitives on top, because that live-lock will percolate through. > > Do you mean the below implementation has live-lock risk? > > +static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail) > > +{ > > + u32 old, new, val = atomic_read(&lock->val); > > + > > + for (;;) { > > + new = (val & _Q_LOCKED_PENDING_MASK) | tail; > > + old = atomic_cmpxchg(&lock->val, val, new); > > + if (old == val) > > + break; > > + > > + val = old; > > + } > > + return old; > > +} > If there is a continuous stream of incoming spinlock takers, it is > possible that some cpus may have to wait a long time to set the tail > right. However, this should only happen on artificial workload. I doubt > it will happen with real workload or with limit number of cpus. Yes, I think is ok for LR/SC in riscv, becasue CPU0 LR CPU1 LR CPU0 SC //success CPU1 SC //fail or CPU0 LR CPU1 LR CPU1 SC //success CPU0 SC //fail So always one store condition would success. I think it's OK. > > > >> Step 1 would be to get your architecute fixed such that it can provide > >> fwd progress guarantees for LL/SC. Otherwise there's absolutely no point > >> in building complex systems with it. > > Quote Waiman's comment [1] on xchg16 optimization: > > > > "This optimization is needed to make the qspinlock achieve performance > > parity with ticket spinlock at light load." > > > > [1] https://lore.kernel.org/kvm/1429901803-29771-6-git-send-email-Waiman.Long@hp.com/ > > > > So for a non-xhg16 machine: > > - ticket-lock for small numbers of CPUs > > - qspinlock for large numbers of CPUs > > > > Okay, I'll put all of them into the next patch :P > > > It is true that qspinlock may not offer much advantage when the number > of cpus is small. It shines for systems with many cpus. You may use > NR_CPUS to determine if the default should be ticket or qspinlock with > user override. To determine the right NR_CPUS threshold, you may need to > run on real SMP RISCV systems to find out. I Agree -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv