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From: Guo Ren <guoren@kernel.org>
To: guoren@kernel.org
Cc: andy.chiu@sifive.com, aou@eecs.berkeley.edu, ardb@kernel.org,
	 greentime.hu@sifive.com, jbaron@akamai.com, jpoimboe@kernel.org,
	 kernel@esmil.dk, linux-riscv@lists.infradead.org,
	mingo@redhat.com,  palmer@dabbelt.com, paul.walmsley@sifive.com,
	peterz@infradead.org,  rostedt@goodmis.org, zong.li@sifive.com,
	Guo Ren <guoren@linux.alibaba.com>
Subject: Re: [PATCH RFC v2 riscv/for-next 5/5] riscv: align arch_static_branch function
Date: Sun, 18 Sep 2022 07:49:29 +0800	[thread overview]
Message-ID: <CAJF2gTRwH33CcRDOy3ngQ6KCTOLAR6VNdBOOT+eykBCoLojjQg@mail.gmail.com> (raw)
In-Reply-To: <20220917183849.589593-1-guoren@kernel.org>

On Sun, Sep 18, 2022 at 2:39 AM <guoren@kernel.org> wrote:
>
> From: Guo Ren <guoren@linux.alibaba.com>
>
> Reduce size of static branch.
>
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Signed-off-by: Guo Ren <guoren@kernel.org>
> ---
>  arch/riscv/include/asm/jump_label.h | 17 ++++++++++-----
>  arch/riscv/kernel/jump_label.c      | 32 +++++++++++++++++++++++++++++
>  2 files changed, 44 insertions(+), 5 deletions(-)
>
> diff --git a/arch/riscv/include/asm/jump_label.h b/arch/riscv/include/asm/jump_label.h
> index 38af2ec7b9bf..78f747dfa8a2 100644
> --- a/arch/riscv/include/asm/jump_label.h
> +++ b/arch/riscv/include/asm/jump_label.h
> @@ -12,17 +12,21 @@
>  #include <linux/types.h>
>  #include <asm/asm.h>
>
> +#ifdef CONFIG_RISCV_ISA_C
> +#define JUMP_LABEL_NOP_SIZE 2
> +#else
>  #define JUMP_LABEL_NOP_SIZE 4
> +#endif
>
>  static __always_inline bool arch_static_branch(struct static_key *key,
>                                                bool branch)
>  {
>         asm_volatile_goto(
> -               "       .option push                            \n\t"
> -               "       .option norelax                         \n\t"
> -               "       .option norvc                           \n\t"
> +#ifdef CONFIG_RISCV_ISA_C
> +               "1:     c.nop                                   \n\t"
> +#else
>                 "1:     nop                                     \n\t"
> -               "       .option pop                             \n\t"
> +#endif
>                 "       .pushsection    __jump_table, \"aw\"    \n\t"
>                 "       .align          " RISCV_LGPTR "         \n\t"
>                 "       .long           1b - ., %l[label] - .   \n\t"
> @@ -39,11 +43,14 @@ static __always_inline bool arch_static_branch_jump(struct static_key *key,
>                                                     bool branch)
>  {
>         asm_volatile_goto(
> +#ifdef CONFIG_RISCV_ISA_C
> +               "1:     c.j             %l[label]               \n\t"
> +#else
>                 "       .option push                            \n\t"
>                 "       .option norelax                         \n\t"
> -               "       .option norvc                           \n\t"
>                 "1:     jal             zero, %l[label]         \n\t"
>                 "       .option pop                             \n\t"
> +#endif
>                 "       .pushsection    __jump_table, \"aw\"    \n\t"
>                 "       .align          " RISCV_LGPTR "         \n\t"
>                 "       .long           1b - ., %l[label] - .   \n\t"
> diff --git a/arch/riscv/kernel/jump_label.c b/arch/riscv/kernel/jump_label.c
> index e6694759dbd0..64a4e5df093d 100644
> --- a/arch/riscv/kernel/jump_label.c
> +++ b/arch/riscv/kernel/jump_label.c
> @@ -11,21 +11,52 @@
>  #include <asm/bug.h>
>  #include <asm/patch.h>
>
> +#ifdef CONFIG_RISCV_ISA_C
> +#define RISCV_INSN_C_NOP 0x0001U
> +#define RISCV_INSN_C_JAL 0xa001U
> +#else
>  #define RISCV_INSN_NOP 0x00000013U
>  #define RISCV_INSN_JAL 0x0000006fU
> +#endif
>
>  void arch_jump_label_transform(struct jump_entry *entry,
>                                enum jump_label_type type)
>  {
>         void *addr = (void *)jump_entry_code(entry);
> +#ifdef CONFIG_RISCV_ISA_C
> +       u16 insn;
> +#else
>         u32 insn;
> +#endif
>
>         if (type == JUMP_LABEL_JMP) {
>                 long offset = jump_entry_target(entry) - jump_entry_code(entry);
> +#ifdef CONFIG_RISCV_ISA_C
> +               if (WARN_ON(offset & 1 || offset < -2048 || offset >= 2048))
> +                       return;
>
> +               /*
> +                * 001 | imm[11|4|9:8|10|6|7|3:1|5] 01 - C.JAL
> +                */
> +               insn = RISCV_INSN_C_JAL |
> +                       (((u16)offset & GENMASK(5, 5)) >> (5 - 2)) |
> +                       (((u16)offset & GENMASK(3, 1)) << (3 - 1)) |
> +                       (((u16)offset & GENMASK(7, 7)) >> (7 - 6)) |
> +                       (((u16)offset & GENMASK(6, 6)) << (7 - 6)) |
> +                       (((u16)offset & GENMASK(10, 10)) >> (10 - 8)) |
> +                       (((u16)offset & GENMASK(9, 8)) << (9 - 8)) |
> +                       (((u16)offset & GENMASK(4, 4)) << (11 - 4)) |
> +                       (((u16)offset & GENMASK(11, 11)) << (12 - 11));
> +       } else {
> +               insn = RISCV_INSN_C_NOP;
> +       }
> +#else
>                 if (WARN_ON(offset & 1 || offset < -524288 || offset >= 524288))
For the unify, it also should be:
if (WARN_ON(offset & 1 || offset < -2048 || offset >= 2048))



>                         return;
>
> +               /*
> +                * imm[20|10:1|11|19:12] | rd | 1101111 - JAL
> +                */
>                 insn = RISCV_INSN_JAL |
>                         (((u32)offset & GENMASK(19, 12)) << (12 - 12)) |
>                         (((u32)offset & GENMASK(11, 11)) << (20 - 11)) |
> @@ -34,6 +65,7 @@ void arch_jump_label_transform(struct jump_entry *entry,
>         } else {
>                 insn = RISCV_INSN_NOP;
>         }
> +#endif
>
>         mutex_lock(&text_mutex);
>         patch_text_nosync(addr, &insn, sizeof(insn));
> --
> 2.36.1
>


-- 
Best Regards
 Guo Ren

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  reply	other threads:[~2022-09-17 23:50 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-13  9:42 [PATCH RFC v2 riscv/for-next 0/5] Enable ftrace with kernel preemption for RISC-V Andy Chiu
2022-09-13  9:42 ` [PATCH RFC v2 riscv/for-next 1/5] riscv: align ftrace to 4 Byte boundary and increase ftrace prologue size Andy Chiu
2022-09-15 13:53   ` Guo Ren
2022-09-17  1:15     ` Andy Chiu
2022-09-13  9:42 ` [PATCH RFC v2 riscv/for-next 2/5] riscv: export patch_insn_write Andy Chiu
2022-09-13  9:42 ` [PATCH RFC v2 riscv/for-next 3/5] riscv: ftrace: use indirect jump to work with kernel preemption Andy Chiu
2022-09-14 13:45   ` Guo Ren
2022-09-15 13:30     ` Guo Ren
2022-09-17  1:04     ` Andy Chiu
2022-09-17 10:56       ` Guo Ren
2024-02-20 14:17   ` Evgenii Shatokhin
2022-09-13  9:42 ` [PATCH RFC v2 riscv/for-next 4/5] riscv: ftrace: do not use stop_machine to update code Andy Chiu
2022-09-13  9:42 ` [PATCH RFC v2 riscv/for-next 5/5] riscv: align arch_static_branch function Andy Chiu
2022-09-14 14:06   ` Guo Ren
2022-09-16 23:54     ` Andy Chiu
2022-09-17  0:22       ` Guo Ren
2022-09-17 18:17         ` [PATCH] riscv: jump_label: Optimize size with RISCV_ISA_C guoren
2022-09-17 18:38         ` [PATCH RFC v2 riscv/for-next 5/5] riscv: align arch_static_branch function guoren
2022-09-17 23:49           ` Guo Ren [this message]
2022-09-17 23:59           ` Guo Ren
2022-09-18  0:12           ` Jessica Clarke
2022-09-18  0:46             ` Guo Ren
2022-09-14 14:24   ` Jessica Clarke
2022-09-15  1:47     ` Guo Ren
2022-09-15  2:34       ` Jessica Clarke
2024-02-13 19:42 ` [PATCH RFC v2 riscv/for-next 0/5] Enable ftrace with kernel preemption for RISC-V Evgenii Shatokhin
2024-02-21  5:27   ` Andy Chiu
2024-02-21 16:55     ` Evgenii Shatokhin
2024-03-06 20:57       ` Alexandre Ghiti
2024-03-07  8:35         ` Evgenii Shatokhin
2024-03-07 12:27         ` Andy Chiu
2024-03-07 13:21           ` Alexandre Ghiti
2024-03-07 15:57             ` Samuel Holland
2024-03-11 14:24               ` Andy Chiu
2024-03-19 14:50                 ` Alexandre Ghiti
2024-03-19 14:58                   ` Conor Dooley
2024-03-20 16:37                   ` Andy Chiu
2024-03-18 15:31       ` Andy Chiu
2024-03-19 15:32         ` Evgenii Shatokhin
2024-03-20 16:38           ` Andy Chiu
2024-03-19 17:37         ` Alexandre Ghiti
2024-03-20 16:36           ` Andy Chiu
2024-03-21 11:02             ` Alexandre Ghiti

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