From: Guo Ren <guoren@kernel.org>
To: Arnd Bergmann <arnd@arndb.de>
Cc: Peter Zijlstra <peterz@infradead.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-csky@vger.kernel.org,
linux-arch <linux-arch@vger.kernel.org>,
Guo Ren <guoren@linux.alibaba.com>,
Will Deacon <will@kernel.org>, Ingo Molnar <mingo@redhat.com>,
Waiman Long <longman@redhat.com>,
Anup Patel <anup@brainfault.org>,
Sebastian Andrzej Siewior <sebastian@breakpoint.cc>
Subject: Re: [PATCH v4 3/4] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
Date: Tue, 30 Mar 2021 10:26:19 +0800 [thread overview]
Message-ID: <CAJF2gTSpnHndT9NkrzvNP6xvqV51_DENwh2BHaduUnGyUE=Jaw@mail.gmail.com> (raw)
In-Reply-To: <CAK8P3a3jpQ7dDiVG0s_DQiL6n_MdnhYHMjqFfJ92JJBJFPQZPQ@mail.gmail.com>
On Mon, Mar 29, 2021 at 9:56 PM Arnd Bergmann <arnd@arndb.de> wrote:
>
> On Mon, Mar 29, 2021 at 2:52 PM Guo Ren <guoren@kernel.org> wrote:
> >
> > On Mon, Mar 29, 2021 at 7:31 PM Peter Zijlstra <peterz@infradead.org> wrote:
> > >
> > > On Mon, Mar 29, 2021 at 01:16:53PM +0200, Peter Zijlstra wrote:
> > > > Anyway, an additional 'funny' is that I suspect you cannot prove fwd
> > > > progress of the entire primitive with any of this on. But who cares
> > > > about details anyway.. :/
> > >
> > > What's the architectural guarantee on LL/SC progress for RISC-V ?
> >
> > funct5 | aq | rl | rs2 | rs1 | funct3 | rd | opcode
> > 5 1 1 5 5 3 5 7
> > LR.W/D ordering 0 addr width dest AMO
> > SC.W/D ordering src addr width dest AMO
> >
> > LR.W loads a word from the address in rs1, places the sign-extended
> > value in rd, and registers a reservation set—a set of bytes that
> > subsumes the bytes in the addressed word. SC.W conditionally writes a
> > word in rs2 to the address in rs1: the SC.W succeeds only if the
> > reservation is still valid and the reservation set contains the bytes
> > being written. If the SC.W succeeds, the instruction writes the word
> > in rs2 to memory, and it writes zero to rd. If the SC.W fails, the
> > instruction does not write to memory, and it writes a nonzero value to
> > rd. Regardless of success or failure, executing an SC.W instruction
> > *invalidates any reservation held by this hart*.
> >
> > More details, ref:
> > https://github.com/riscv/riscv-isa-manual
>
> I think section "3.5.3.2 Reservability PMA" [1] would be a more relevant
> link, as this defines memory areas that either do or do not have
> forward progress guarantees, including this part:
>
> "When LR/SC is used for memory locations marked RsrvNonEventual,
> software should provide alternative fall-back mechanisms used when
> lack of progress is detected."
>
> My reading of this is that if the example you tried stalls, then either
> the PMA is not RsrvEventual, and it is wrong to rely on ll/sc on this,
> or that the PMA is marked RsrvEventual but the implementation is
> buggy.
Yes, PMA just defines physical memory region attributes, But in our
processor, when MMU is enabled (satp's value register > 2) in s-mode,
it will look at our custom PTE's attributes BIT(63) ref [1]:
PTE format:
| 63 | 62 | 61 | 60 | 59 | 58-8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SO C B SH SE RSW D A G U X W R V
^ ^ ^ ^ ^
BIT(63): SO - Strong Order
BIT(62): C - Cacheable
BIT(61): B - Bufferable
BIT(60): SH - Shareable
BIT(59): SE - Security
So the memory also could be RsrvNone/RsrvEventual.
[1] https://github.com/c-sky/csky-linux/commit/e837aad23148542771794d8a2fcc52afd0fcbf88
>
> It also seems that the current "amoswap" based implementation
> would be reliable independent of RsrvEventual/RsrvNonEventual.
Yes, the hardware implementation of AMO could be different from LR/SC.
AMO could use ACE snoop holding to lock the bus in hw coherency
design, but LR/SC uses an exclusive monitor without locking the bus.
> arm64 is already in the situation of having to choose between
> two cmpxchg() implementation at runtime to allow falling back to
> a slower but more general version, but it's best to avoid that if you
> can.
Current RISC-V needn't multiple versions to select, and all AMO &
LR/SC has been defined in the spec.
RISC-V hasn't CAS instructions, and it uses LR/SC for cmpxchg. I don't
think LR/SC would be slower than CAS, and CAS is just good for code
size.
>
> Arnd
>
> [1] http://www.five-embeddev.com/riscv-isa-manual/latest/machine.html#atomicity-pmas
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
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next prev parent reply other threads:[~2021-03-30 2:27 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-27 18:06 [PATCH v4 0/4] riscv: Add qspinlock/qrwlock guoren
2021-03-27 18:06 ` [PATCH v4 1/4] riscv: cmpxchg.h: Cleanup unused code guoren
2021-03-27 18:06 ` [PATCH v4 2/4] riscv: cmpxchg.h: Merge macros guoren
2021-03-27 21:25 ` Arnd Bergmann
2021-03-28 1:50 ` Guo Ren
2021-03-27 18:06 ` [PATCH v4 3/4] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 guoren
2021-03-27 18:43 ` Waiman Long
2021-03-28 1:48 ` Guo Ren
2021-03-29 7:50 ` Peter Zijlstra
2021-03-29 9:41 ` Arnd Bergmann
2021-03-29 11:16 ` Peter Zijlstra
2021-03-29 11:29 ` Peter Zijlstra
2021-03-29 12:52 ` Guo Ren
2021-03-29 13:56 ` Arnd Bergmann
2021-03-30 2:26 ` Guo Ren [this message]
2021-03-30 5:51 ` Anup Patel
2021-03-30 6:26 ` Guo Ren
2021-03-30 7:11 ` Arnd Bergmann
2021-03-31 4:18 ` Guo Ren
2021-03-31 5:33 ` Paul Campbell
2021-04-05 16:12 ` Guo Ren
2021-03-31 6:44 ` Guo Ren
2021-03-31 7:12 ` Arnd Bergmann
2021-03-29 11:19 ` Guo Ren
2021-03-29 11:26 ` Peter Zijlstra
2021-03-29 12:01 ` Guo Ren
2021-03-29 12:49 ` Peter Zijlstra
2021-03-30 3:13 ` Guo Ren
2021-03-30 4:54 ` Anup Patel
2021-03-30 6:27 ` Guo Ren
2021-03-30 8:31 ` David Laight
2021-03-30 14:09 ` Waiman Long
2021-03-31 14:47 ` Guo Ren
2021-04-05 16:45 ` Guo Ren
2021-03-30 16:08 ` Peter Zijlstra
2021-03-30 22:35 ` Stafford Horne
2021-03-31 7:23 ` Arnd Bergmann
2021-03-31 12:31 ` Stafford Horne
2021-03-31 15:10 ` Guo Ren
2021-04-06 8:51 ` Stafford Horne
2021-04-06 3:50 ` Guo Ren
2021-04-06 8:56 ` Stafford Horne
2021-04-07 8:42 ` Arnd Bergmann
2021-04-07 11:36 ` Peter Zijlstra
2021-04-07 11:57 ` Arnd Bergmann
2021-04-07 12:02 ` Peter Zijlstra
2021-04-05 16:40 ` Guo Ren
2021-03-31 15:22 ` Guo Ren
2021-04-06 7:15 ` Peter Zijlstra
2021-04-07 9:42 ` Christoph Hellwig
2021-04-07 14:29 ` Christoph Müllner
2021-04-07 14:34 ` Christoph Hellwig
2021-04-07 15:51 ` Peter Zijlstra
2021-04-07 16:44 ` Peter Zijlstra
2021-04-07 15:52 ` Peter Zijlstra
2021-04-07 16:54 ` Peter Zijlstra
2021-04-07 16:00 ` Peter Zijlstra
2021-04-07 19:50 ` Christoph Müllner
2021-04-06 17:24 ` Boqun Feng
2021-04-07 9:26 ` Peter Zijlstra
2021-03-29 12:13 ` Anup Patel
2021-03-29 12:54 ` Peter Zijlstra
2021-03-27 18:06 ` [PATCH v4 4/4] riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock guoren
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