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Tue, 24 Nov 2020 16:52:36 -0800 (PST) X-Gm-Message-State: AOAM531rlCzv9SfnoL1HphiBvlFHM4R5iQCJlmnwUZGVtNsB+0CX6u4n C1AC/ZypyQ5z7DkbKBzSJO+AQiRCqBPWIsGebwA= X-Google-Smtp-Source: ABdhPJxXNypMXNrwvl404YxnwDVGzaYXnO59TiupDEKcpkPWd6NZwPa2V/R/J4KGCf3GcXUkVvM9vFT0gdbbTku0XNk= X-Received: by 2002:a05:651c:213:: with SMTP id y19mr325504ljn.250.1606265554826; Tue, 24 Nov 2020 16:52:34 -0800 (PST) MIME-Version: 1.0 References: <1606225437-22948-1-git-send-email-guoren@kernel.org> <1606225437-22948-2-git-send-email-guoren@kernel.org> <20201124143931.GI2414@hirez.programming.kicks-ass.net> In-Reply-To: <20201124143931.GI2414@hirez.programming.kicks-ass.net> From: Guo Ren Date: Wed, 25 Nov 2020 08:52:23 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 2/5] riscv: Add QUEUED_SPINLOCKS & QUEUED_RWLOCKS supported To: Peter Zijlstra X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201124_195238_786146_C1DE1CF3 X-CRM114-Status: GOOD ( 18.06 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Guo Ren , Arnd Bergmann , Anup Patel , Palmer Dabbelt , Linux Kernel Mailing List , linux-csky@vger.kernel.org, Michael Clark , Paul Walmsley , linux-riscv Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Thx Peter, On Tue, Nov 24, 2020 at 10:39 PM Peter Zijlstra wrote: > > On Tue, Nov 24, 2020 at 01:43:54PM +0000, guoren@kernel.org wrote: > > diff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuild > > index 59dd7be..6f5f438 100644 > > --- a/arch/riscv/include/asm/Kbuild > > +++ b/arch/riscv/include/asm/Kbuild > > @@ -6,3 +6,6 @@ generic-y += kvm_para.h > > generic-y += local64.h > > generic-y += user.h > > generic-y += vmlinux.lds.h > > +generic-y += mcs_spinlock.h > > +generic-y += qrwlock.h > > +generic-y += qspinlock.h > > diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h > > index 5609185..e178700 100644 > > --- a/arch/riscv/include/asm/cmpxchg.h > > +++ b/arch/riscv/include/asm/cmpxchg.h > > @@ -16,7 +16,43 @@ > > __typeof__(ptr) __ptr = (ptr); \ > > __typeof__(new) __new = (new); \ > > __typeof__(*(ptr)) __ret; \ > > + register unsigned long __rc, tmp, align, addr; \ > > switch (size) { \ > > + case 2: \ > > + align = ((unsigned long) __ptr & 0x3); \ > > + addr = ((unsigned long) __ptr & ~0x3); \ > > + if (align) { \ > > + __asm__ __volatile__ ( \ > > + "0: lr.w %0, 0(%z4)\n" \ > > + " move %1, %0\n" \ > > + " slli %1, %1, 16\n" \ > > + " srli %1, %1, 16\n" \ > > + " move %2, %z3\n" \ > > + " slli %2, %2, 16\n" \ > > + " or %1, %2, %1\n" \ > > + " sc.w %2, %1, 0(%z4)\n" \ > > + " bnez %2, 0b\n" \ > > + " srli %0, %0, 16\n" \ > > + : "=&r" (__ret), "=&r" (tmp), "=&r" (__rc) \ > > + : "rJ" (__new), "rJ"(addr) \ > > + : "memory"); \ > > + } else { \ > > + __asm__ __volatile__ ( \ > > + "0: lr.w %0, (%z4)\n" \ > > + " move %1, %0\n" \ > > + " srli %1, %1, 16\n" \ > > + " slli %1, %1, 16\n" \ > > + " move %2, %z3\n" \ > > + " or %1, %2, %1\n" \ > > + " sc.w %2, %1, 0(%z4)\n" \ > > + " bnez %2, 0b\n" \ > > + " slli %0, %0, 16\n" \ > > + " srli %0, %0, 16\n" \ > > + : "=&r" (__ret), "=&r" (tmp), "=&r" (__rc) \ > > + : "rJ" (__new), "rJ"(addr) \ > > + : "memory"); \ > > + } \ > > + break; \ > > case 4: \ > > __asm__ __volatile__ ( \ > > " amoswap.w %0, %2, %1\n" \ > > I'm pretty sure there's a handfull of implementations like this out > there... if only we could share. Michael has sent qspinlock before, ref to Link below. He reused mips' code. Link: https://lore.kernel.org/linux-riscv/20190211043829.30096-1-michaeljclark@mac.com/ Which short xchg implementation do you prefer (Mine or his)? > > Anyway, this too should be an independent patch. Ok, I'll separate it into two patches, 1. implement short xchg 2. qspinlock enabled based on Michael's patch -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv