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Tue, 13 Apr 2021 22:54:29 -0700 (PDT) MIME-Version: 1.0 References: <20210413104503.GD15806@arm.com> <73cab48b63ea4ba3b1ef532f47d146f4@AcuMS.aculab.com> In-Reply-To: <73cab48b63ea4ba3b1ef532f47d146f4@AcuMS.aculab.com> From: Guo Ren Date: Wed, 14 Apr 2021 13:54:18 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] riscv: locks: introduce ticket-based spinlock implementation To: David Laight Cc: Catalin Marinas , =?UTF-8?Q?Christoph_M=C3=BCllner?= , Peter Zijlstra , Palmer Dabbelt , Anup Patel , linux-riscv , Linux Kernel Mailing List , Guo Ren , "will.deacon@arm.com" , Arnd Bergmann X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210413_225432_624359_C000F51B X-CRM114-Status: GOOD ( 13.25 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Apr 13, 2021 at 6:54 PM David Laight wrote: > > From: Catalin Marinas > > Sent: 13 April 2021 11:45 > ... > > This indeed needs some care. IIUC RISC-V has similar restrictions as arm > > here, no load/store instructions are allowed between LR and SC. You > > can't guarantee that the compiler won't spill some variable onto the > > stack. > > You can probably never guarantee the compiler won't spill to stack. > Especially if someone compiles with -O0. > > Which probably means that anything using LR/SC must be written in > asm and the C wrappers disabled. Agree, and cmpxchg has been widely used in Linux. I think it's the last requirement for complex atomic API, although cmpxchg has ABA problem: CPU0 CPU1 ======= ====== do { old32 = load32; *ptr32 = new32_tmp; *ptr32 = old32; load32 = cmpxchg(ptr32, old32, new32); //still success } while (load32 != old32); That means cmpxhg only cares about the result but not the middle situation. It's different from LR/SC or AMO instructions. > > David > > - > Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK > Registration No: 1397386 (Wales) > -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv