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Mon, 14 Nov 2022 03:38:34 -0800 (PST) X-Google-Smtp-Source: AA0mqf6L9mlzJuF+4ajrjjasX5OxkT3zApkEGykXisk+djB1Nw9RrvY1XIhkkZfvgeCt+XXOQ4LQv/dZX4JCRuVeKlM= X-Received: by 2002:a81:556:0:b0:378:5e3a:8fad with SMTP id 83-20020a810556000000b003785e3a8fadmr12450100ywf.78.1668425914288; Mon, 14 Nov 2022 03:38:34 -0800 (PST) MIME-Version: 1.0 References: <20221110164924.529386-1-heiko@sntech.de> <20221110164924.529386-6-heiko@sntech.de> <20221114113553.3dxrumhk72jouzek@kamzik> In-Reply-To: <20221114113553.3dxrumhk72jouzek@kamzik> From: Emil Renner Berthing Date: Mon, 14 Nov 2022 12:38:17 +0100 Message-ID: Subject: Re: [PATCH 5/7] RISC-V: fix auipc-jalr addresses in patched alternatives To: Andrew Jones Cc: Heiko Stuebner , linux-riscv@lists.infradead.org, palmer@dabbelt.com, christoph.muellner@vrull.eu, prabhakar.csengg@gmail.com, conor@kernel.org, philipp.tomsich@vrull.eu, Heiko Stuebner X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221114_033853_507000_925B35DC X-CRM114-Status: GOOD ( 17.91 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, 14 Nov 2022 at 12:35, Andrew Jones wrote: > > On Mon, Nov 14, 2022 at 11:57:29AM +0100, Emil Renner Berthing wrote: > > On Thu, 10 Nov 2022 at 17:50, Heiko Stuebner wrote: > ... > > > @@ -316,8 +384,15 @@ void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin, > > > } > > > > > > tmp = (1U << alt->errata_id); > > > - if (cpu_req_feature & tmp) > > > - patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len); > > > + if (cpu_req_feature & tmp) { > > > + /* do the basic patching */ > > > + patch_text_nosync(alt->old_ptr, alt->alt_ptr, > > > + alt->alt_len); > > > + > > > + riscv_alternative_fix_auipc_jalr(alt->old_ptr, > > > + alt->alt_len, > > > + alt->old_ptr - alt->alt_ptr); > > > > Here you're casting a void pointer to an instruction to an unsigned > > int pointer, but since we enable compressed instructions this may > > result in an unaligned pointer. Using this pointer will work, but may > > be slow. Eg. fault to m-mode to be patched up. We already do that in > > other places in the arch/riscv, but I'd prefer not to add new > > instances of this. > > Alternative instruction sequences (old and new) have compression disabled. I see, but if the instructions before the alternative sequence ends on an unaligned address will there be inserted 16bit NOPs to make sure the alternative sequence will be aligned? > Thanks, > drew _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv