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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Emil Renner Berthing , Palmer Dabbelt , Paul Walmsley , Albert Ou , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Sagar Kadam , Yanhong Wang , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, kernel@collabora.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230215_051145_164590_93FC7407 X-CRM114-Status: GOOD ( 30.21 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, 14 Feb 2023 at 21:42, Conor Dooley wrote: > > Hey all, > > On Sat, Feb 11, 2023 at 05:18:10AM +0200, Cristian Ciocaltea wrote: > > Document the compatible for the SiFive Composable Cache Controller found > > on the StarFive JH7100 SoC. > > > > This also requires extending the 'reg' property to handle distinct > > ranges, as specified via 'reg-names'. > > > > Signed-off-by: Cristian Ciocaltea > > --- > > .../bindings/riscv/sifive,ccache0.yaml | 28 ++++++++++++++++++- > > 1 file changed, 27 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml > > index 31d20efaa6d3..2b864b2f12c9 100644 > > --- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml > > +++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml > > @@ -25,6 +25,7 @@ select: > > - sifive,ccache0 > > - sifive,fu540-c000-ccache > > - sifive,fu740-c000-ccache > > + - starfive,jh7100-ccache > > > > required: > > - compatible > > @@ -37,6 +38,7 @@ properties: > > - sifive,ccache0 > > - sifive,fu540-c000-ccache > > - sifive,fu740-c000-ccache > > + - starfive,jh7100-ccache > > - const: cache > > - items: > > - const: starfive,jh7110-ccache > > @@ -70,7 +72,13 @@ properties: > > - description: DirFail interrupt > > > > reg: > > - maxItems: 1 > > + minItems: 1 > > + maxItems: 2 > > + > > + reg-names: > > + items: > > + - const: control > > + - const: sideband > > So why is this called "sideband"? > In the docs for the JH7100 it is called LIM & it's called LIM in our > docs for the PolarFire SoC (at the same address btw) and we run the HSS > out of it! LIM being "loosely integrated memory", which by the limit > hits on Google may be a SiFive-ism? > > I'm not really sure if adding it as a "reg" section is the right thing > to do as it's not "just" a register bank. > Perhaps Rob/Krzysztof have a take on that one? Yes, this seems to be a leftover I didn't manage to clean up yet. The "sideband" range is called L2 LIM in the datasheet and seems to be a way to use the cache directly. The Sifive docs read "When cache ways are disabled, they are addressable in the L2 Loosely-Integrated Memory (L2 LIM) address space [..]". This feature is not used by Linux on the JH7100, so can just be removed here. /Emil > > > > next-level-cache: true > > > > @@ -89,6 +97,7 @@ allOf: > > contains: > > enum: > > - sifive,fu740-c000-ccache > > + - starfive,jh7100-ccache > > - starfive,jh7110-ccache > > - microchip,mpfs-ccache > > > > @@ -106,12 +115,29 @@ allOf: > > Must contain entries for DirError, DataError and DataFail signals. > > maxItems: 3 > > > > + - if: > > + properties: > > + compatible: > > + contains: > > + const: starfive,jh7100-ccache > > + > > + then: > > + properties: > > + reg: > > + maxItems: 2 > > + > > + else: > > + properties: > > + reg: > > + maxItems: 1 > > + > > - if: > > properties: > > compatible: > > contains: > > enum: > > - sifive,fu740-c000-ccache > > + - starfive,jh7100-ccache > > - starfive,jh7110-ccache > > > > then: > > -- > > 2.39.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv