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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=zj5nVV7hFwHQ61cfvcd7q5vRxcIEvVb9YfJiy7fOWvA=; b=l0cvB2oQmlryb/KOmKndYib7QeoFX3B+8C/L3+dXYqEvabL73YqtQYl+8wMBASBmUK Vg83ATAJ1B4YIx9498zMNDiQc1Q3D1M7elS5H7trEW7kK80DHL0EL/F9DuuEz+stEfgR vfc4L4vpnOXvsiuV9ZdeN/bkGPBWLThmUjss4Uk7pK6Zqfvx24f8iargaR6ls7kDE/7l JrPdiA9ETNWuRGmP9ma0HnTO6hI2XfUpxTHEUMEWbQMWZwbUxLTbpZPtXp9sFxyya0NL 7hjBjusDAZF4aOF2GWO3QRS1yfmrCJw8M7AwsSFTvfC+ijVlQJxXYUh1d3Pi37M/PtGt vkpg== X-Gm-Message-State: APjAAAUK8FrAvw/Q26nye6ynQkvoPoMhSJVrKCNy8RBCHhxo4xJpEhzw 76wk9BtRr1TQQ7MVAdH2d33aii07S8tav5Bw+ue3+Q== X-Google-Smtp-Source: APXvYqzyeDjr5TTdOJAdTcs2Mr8QC5C9jpLr0O1hsPKOR4KROaGVbyvqfBoBKMTT9YtrQzx5v4HhQifzo5shXhGLKpw= X-Received: by 2002:a92:4555:: with SMTP id s82mr1356329ila.228.1573092702728; Wed, 06 Nov 2019 18:11:42 -0800 (PST) MIME-Version: 1.0 References: <20191028075658.12143-1-green.wan@sifive.com> <20191028075658.12143-4-green.wan@sifive.com> <20191105174823.GF952516@vkoul-mobl> In-Reply-To: <20191105174823.GF952516@vkoul-mobl> From: Green Wan Date: Thu, 7 Nov 2019 10:11:33 +0800 Message-ID: Subject: Re: [PATCH v5 3/4] dmaengine: sf-pdma: add platform DMA support for HiFive Unleashed A00 To: Vinod Koul X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191106_181144_279721_0DA31688 X-CRM114-Status: GOOD ( 23.17 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Albert Ou , kbuild test robot , Greg Kroah-Hartman , Palmer Dabbelt , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Bin Meng , dmaengine@vger.kernel.org, Yash Shah , Rob Herring , Sagar Kadam , Jonathan Cameron , Paul Walmsley , Mauro Carvalho Chehab , Dan Williams , "Paul E. McKenney" , "David S. Miller" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Nov 6, 2019 at 1:48 AM Vinod Koul wrote: > > On 28-10-19, 15:56, Green Wan wrote: > > Add PDMA driver, sf-pdma, to enable DMA engine on HiFive Unleashed > > Rev A00 board. > > > > - Implement dmaengine APIs, support MEM_TO_MEM async copy. > > - Tested by DMA Test client > > - Supports 4 channels DMA, each channel has 1 done and 1 err > > interrupt connected to platform-level interrupt controller (PLIC). > > - Depends on DMA_ENGINE and DMA_VIRTUAL_CHANNELS > > > > The datasheet is here: > > > > https://static.dev.sifive.com/FU540-C000-v1.0.pdf > > > > Follow the DMAengine controller doc, > > "./Documentation/driver-api/dmaengine/provider.rst" to implement DMA > > engine. And use the dma test client in doc, > > "./Documentation/driver-api/dmaengine/dmatest.rst", to test. > > > > Each DMA channel has separate HW regs and support done and error ISRs. > > 4 channels share 1 done and 1 err ISRs. There's no expander/arbitrator > > in DMA HW. > > > > ------ ------ > > | |--< done 23 >--|ch 0| > > | |--< err 24 >--| | (dma0chan0) > > | | ------ > > | | ------ > > | |--< done 25 >--|ch 1| > > | |--< err 26 >--| | (dma0chan1) > > |PLIC| ------ > > | | ------ > > | |--< done 27 >--|ch 2| > > | |--< err 28 >--| | (dma0chan2) > > | | ------ > > | | ------ > > | |--< done 29 >--|ch 3| > > | |--< err 30 >--| | (dma0chan3) > > ------ ------ > > > > Reviewed-by: Vinod Koul > > when did i provide this? > > > Signed-off-by: Green Wan > > Reported-by: kbuild test robot > > Fixes: 31c3b98b5a01 ("dmaengine: sf-pdma: add platform DMA support for HiFive Unleashed A00") > > Fixes what... this is not a upstream commit? > Since I received a RFC patch from kbuild with the fix commit number I thought it was about merged. RFC requested to add the "Reported-by" and "Fixes" but looks miss the contributor so I added them as well. I'll remove them in next submit. Sorry for causing confusion. > > Signed-off-by: kbuild test robot > > --- > > Please list the changes done from prev version, here or in cover letter > will add change log. > > +static struct sf_pdma_desc *sf_pdma_alloc_desc(struct sf_pdma_chan *chan) > > +{ > > + struct sf_pdma_desc *desc; > > + unsigned long flags; > > + > > + spin_lock_irqsave(&chan->lock, flags); > > + > > + if (chan->desc && !chan->desc->in_use) { > > + spin_unlock_irqrestore(&chan->lock, flags); > > + return chan->desc; > > + } > > + > > + spin_unlock_irqrestore(&chan->lock, flags); > > + > > + desc = kzalloc(sizeof(*desc), GFP_NOWAIT); > > + > > this empty line in not required > > > +static struct dma_async_tx_descriptor * > > + sf_pdma_prep_dma_memcpy(struct dma_chan *dchan, > > + dma_addr_t dest, > > please make it left justified will fix. > > > +static int sf_pdma_slave_config(struct dma_chan *dchan, > > + struct dma_slave_config *cfg) > > +{ > > + struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan); > > + > > + memcpy(&chan->cfg, cfg, sizeof(*cfg)); > > + chan->dma_dir = DMA_MEM_TO_MEM; > > ?? looking at changelog we have only memcpy support, so this should not > be here, pls remove this. > > > +static enum dma_status > > +sf_pdma_tx_status(struct dma_chan *dchan, > > + dma_cookie_t cookie, > > + struct dma_tx_state *txstate) > > +{ > > + struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan); > > + enum dma_status status; > > + > > + status = dma_cookie_status(dchan, cookie, txstate); > > + > > + if (txstate && status != DMA_ERROR) > > + dma_set_residue(txstate, sf_pdma_desc_residue(chan)); > > which residue? the query can be for a cookie which is still in pending > list! you need to check the cookie and only read register for cookie if > submitted > WIll fix this. > > +static int sf_pdma_remove(struct platform_device *pdev) > > +{ > > + struct sf_pdma *pdma = platform_get_drvdata(pdev); > > + struct sf_pdma_chan *ch; > > + int i; > > + > > + for (i = 0; i < PDMA_NR_CH; i++) { > > + ch = &pdma->chans[i]; > > + > > + list_del(&ch->vchan.chan.device_node); > > + tasklet_kill(&ch->vchan.task); > > + tasklet_kill(&ch->done_tasklet); > > + tasklet_kill(&ch->err_tasklet); > > you have an isr registered which can fire and schedule tasklets.. will fix it by free irq first. Thanks for reviewing. > -- > ~Vinod _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv