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Thu, 28 Jul 2022 01:14:28 -0700 (PDT) MIME-Version: 1.0 References: <20220724122517.1019187-8-guoren@kernel.org> <202207280822.VHS6qieH-lkp@intel.com> In-Reply-To: From: Arnd Bergmann Date: Thu, 28 Jul 2022 10:14:12 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH V8 07/10] riscv: Add qspinlock support To: Guo Ren Cc: Palmer Dabbelt , =?UTF-8?Q?Heiko_St=C3=BCbner?= , Christoph Hellwig , Arnd Bergmann , Peter Zijlstra , Will Deacon , Boqun Feng , Waiman Long , Ingo Molnar , Philipp Tomsich , Christoph Muellner , Linux Kernel Mailing List , David Laight , clang-built-linux , kbuild-all@lists.01.org, linux-riscv , linux-csky@vger.kernel.org, Guo Ren , Niklas Schnelle X-Provags-ID: V03:K1:7lNKLThPXKfgtZzCcV9fVQeLHSUEG7raIz1cNrwJ1HaJl2lAZS0 TiVlOmYyOPZnql/ngzlbRza+HreXkpWo3/hLuRetK0AD8u6BNkixJUwwUkVgP6Itu0u7NkQ uZdbe8lcv6deJhD8xVPwEa1n8s4B7ThokpKPr/+G+rSXljZngAkscnGHeLfb8HXVbhAE7DY xpgiDrIbLF9BBuXJ3BJnQ== X-UI-Out-Filterresults: notjunk:1;V03:K0:m9S+vPv6q7E=:e8BpMSFBbpQCyKPp1EORmW Seg0CrhDBHGGMwD9DC/nHkufm6AQEtKtL/ZraAIcvsdPlaSlRqqCQs2ZNObpyioCVzYHrETHn jCcZBXF9MrA0m95/iL9yHWBHahDWJdzUYTPC3XdH/9Y1eoHCTvF2s5uzfp0Y1moZ+QiWh5rHk N+IgdDseiD6LpaFzBfgyvutDDc1WU0Fq+1QsSJzEF+1420hWbRBs9N/xbMQrAU+zj0BcxKl9a PbuUQhdyAkxOYELyYIvpGZux2P3wD91MLJiXMOcyHSdAAF16hggRyU8DiEa8DlmxxFsoOYykR 1QNp1iMvKlIZ+km33/+E8gpGrbRWO0iJJqRYCRCzU9atRrAO0BJ56hWlY+yT17nEK5WCjVT2b UmJa7FX3Qg8PQbbRSXH2kt8fXUMgEMaps3sv7BCtWtdUXjXCJOSJVh2168f8H+SONiBAr6FRS xBX7H8VgdMYqwNgsezFWfDXnUb5e36bl8KyifHAJODn6HTlgXB4XCU5XQKK0UCO3t9q7DHQmG LbWoOLD9HVR0SZj/fbMXS1DZfxA+cx8VJMU4grUso1+WQx4u/SDvmwuGKBypYLT1kroKz53au zZt0LN6ra+exHA4C7hJQNMrUaMPae6tKOX8LszcgrcnNyxBoaeij5IINojlYLBLN39y11M2DW Xa/JPJd8Fr51cwuukvaUgtaxfgt+GgLB5L/j7a+QlIVMNwt6niEJ9IHMARNWU6IYA8EJEN1RH Zoda0pDngVUeVbpf4k4e8fd35LGxaRP/ClZKiA== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220728_011440_779846_F0C9422F X-CRM114-Status: GOOD ( 19.20 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Jul 28, 2022 at 5:35 AM Guo Ren wrote: > > Hi Palmer, > > The warning is from a clang problem. > > drivers/net/wireguard/queueing.c: > static void __wg_prev_queue_enqueue(struct prev_queue *queue, struct > sk_buff *skb) > { > WRITE_ONCE(NEXT(skb), NULL); > WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb); > } > > The queue->head is 64bit pointer size. > > #define __xchg_relaxed(ptr, new, size) \ > ({ \ > __typeof__(ptr) __ptr = (ptr); \ > __typeof__(new) __new = (new); \ > __typeof__(*(ptr)) __ret; \ > switch (size) { \ > case 2: { \ > ... Clang shouldn't give warning from here, because code won't enter the path. > break; \ > } \ > case 4: \ > ... > break; \ > case 8: \ > ... The case would enter this path. > break; \ > default: \ > BUILD_BUG(); \ > } \ > __ret; \ > }) I assume it's this warning you are referring to? >> drivers/net/wireguard/queueing.c:68:18: warning: cast to 'typeof (*((__ai_ptr)))' (aka 'struct sk_buff *') from smaller integer type 'unsigned int' [-Wint-to-pointer-cast] WRITE_ONCE(NEXT(xchg_release(&queue->head, skb)), skb); I don't consider this a bug in clang, it just performs the normal type checking before dead code elimination and complains about code that clearly violates the type rules. I would suggest you split out the 16-bit xchg() into a properly typed inline function and add type casts when calling it. In fact, I would love to completely eliminate the 8-bit and 16-bit cases from the regular xchg() and cmpxchg() interface and require all callers to explicitly call the xchg16()/cmpxchg16() instead, as we require for cmpxchg64() on 32-bit architectures already. This is something to do for another time though. > > include/asm-generic/io.h:547:31: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] > > val = __raw_readb(PCI_IOBASE + addr); > > ~~~~~~~~~~ ^ > > include/asm-generic/io.h:560:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic] > > val = __le16_to_cpu((__le16 __force)__raw_readw(PCI_IOBASE + addr)); Not your bug, but I see that CONFIG_MMU=n risc-v has the same bug that s390 has with missing I/O space support. The correct workaround for this is to mark all drivers using PCI I/O space as 'depends on HAS_IO_PORT' or similar and then leaving out the definitions from the asm-generic header. Niklas Schnelle has spent a lot of time working on patches for this, but they are somewhat stuck in review. If RISC-V has the same problem, I hope we can get more people interested in it. I think OpenRISC and C-Sky have this as well, but I'm not sure if there is any plan to upstream clang support for those. Arnd _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv