From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF0E1C433EF for ; Thu, 21 Oct 2021 18:47:35 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6FBAC60EFE for ; Thu, 21 Oct 2021 18:47:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 6FBAC60EFE Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arndb.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Thu, 21 Oct 2021 11:35:10 -0700 (PDT) X-Gm-Message-State: AOAM531TP37jWH8hSNzHor2MX3gD6XGqGrZKER9gEfRQJH+eBnEJko2+ GbCp81o+FYmo9YX3bILfRAXgKo0YmnJLeLwVLN0= X-Google-Smtp-Source: ABdhPJxJnttZVYDDq1wT7sqVg/34xA2ViJzSZlZ8uydGsF2cMPPIn30u8q+0i/QxoA4crgnhZkdmcwVqK+m7oJgBKVg= X-Received: by 2002:a05:600c:1548:: with SMTP id f8mr8597496wmg.35.1634841310501; Thu, 21 Oct 2021 11:35:10 -0700 (PDT) MIME-Version: 1.0 References: <79ae46c3-c028-2c99-2428-b601e4fb03d4@microchip.com> In-Reply-To: From: Arnd Bergmann Date: Thu, 21 Oct 2021 20:34:54 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] soc: add polarfire soc system controller To: Palmer Dabbelt List-Id: Cc: Conor.Dooley@microchip.com, Arnd Bergmann , Olof Johansson , SoC Team , Rob Herring , Damien Le Moal , Jassi Brar , Albert Ou , Paul Walmsley , linux-riscv , "nathan=20Neusch=C3=A4fer?=" , Stephen Rothwell , Cyril.Jean@microchip.com, Daire McNamara , Atish Patra , Nicolas Ferre , Alexandre Belloni , Ludovic Desroches X-Provags-ID: V03:K1:47h3Z3W35bmVNBUFMr8n8sb2DhxJGqFMY4IYevEqtjFASvMAjUH Q3+LKLd3RQRj2wrlO6CM4grz5f4sU5a2BF/dP6B86jrz+aL2+pRGyghwArw5ATiy9CXhzC3 fupEM/oXuIlAnEJuLcXHtlHp9T7ENlI6E5xWssHakrFUdEIq/EKDCVse1Kkcm2+l/xQWO6r E47Wz62IDElfYdOOmtgDw== X-UI-Out-Filterresults: notjunk:1;V03:K0:N2HDL2WKee8=:WPYNlWYhJ8kX73oHlmFsMp ikWD1CCShz1aAxz/yHBq3hwPUJBDdoLNjDr2RTxiKf3lLpjBvxvsWe3ZsPMVfYRvJO3FT/Rg5 ZRt546J5czJSE4CIwjCg5Y4qGeLTHKQLFu3Y7sG537mdHOktkPQEdOLjtVXOQpoP9anAPJuD4 3fGdFU6rYQqrrR9yeMrqJ+z+3FtR5Tes3D+lKGz+mH7XTJS44gt0f06Uk3OdZVYaKICxEpNl7 ixXOw77W6pEtgMQaud9MRAF3qqerUcbC4zGko5awE2WzCkVTCGnT6y1+nG5e/AIF5imJbPjm3 dZ3f1Gtorg1GBjJBRIw3AfkEnTxW2UPgcyTvINRSSUzJpeAkRcmoY9BFzMDxHkjgM1JO9Y7dM Jvpwnhwe80Y2zdp2VJVzh6gP0eyqwuBOKDyZ3n8CwMiKR5IIun4C7+iFPGNqlFcUqFt6SLZ2N i2t479XYZfMTGIqJivYV1LUy9LzU9u6f8fCi0Q9qqfQj9husXjrC6kLvJ9/PNhV/jFMELunfF bdPZ3Qa2+Eu/tEWSP6yWWnBdCa3/CRHvfFKD0r3d860e8cnHUC4pYsrojmLwecA/vaL9ztoVn fru89cPTyzu0d6CQR7+I3S167zvLmkm+pbPrFSy42DcTEo/mqZVyPnMSpLTV9IxskhN1BoZRJ VVVzJUWiEzzu2Bi3mOWhwsnpKFQHrFqWvzl3847/8H89yOO9A59lcY5HMdsUMMkouDe5yCPqv /pQzcf9/FZ50TXlU7XRGAC3xgfwKwrMxTqX+1E5mamhSeRf51j018xp7g3Hl25KGTwo/Lp+qh ERrky6uy/u09j8ZOmmx/0QasQQwzkUALN0/ZkgPV2he9gmBcTE= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211021_113515_662382_4CB21DC6 X-CRM114-Status: GOOD ( 35.09 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, Oct 21, 2021 at 6:00 PM Palmer Dabbelt wrote: > On Thu, 21 Oct 2021 06:13:35 PDT (-0700), Conor.Dooley@microchip.com wrote: > > On 05/10/2021 13:47, conor.dooley@microchip.com wrote: > >> From: Conor Dooley > >> > >> This driver provides an interface for other drivers to access the > >> functions of the system controller on the Microchip PolarFire SoC. > >> > >> Signed-off-by: Conor Dooley > > Is there some extra CCs that I am missing on this patch that weren't > > picked up by getmaintainers, and/or am I mistaken in thinking that > > the soc tree is arm only? We can handle non-Arm SoCs as well, though most architecture maintainers prefer to keep them merged through their trees. > +Arnd, Olof, and the SOC list. They probably understand this better > than I do, we're kind of new to having SOCs in RISC-V land. > > I guess I was assuming that someone maintained drivers/soc, but from > poking around it seems like there's no entry for it and instead it's > just a bunch of entries for the sub-directories. As a result the > scripts aren't picking up anyone to send these too, and I'd assuming > that because they're not in arch/riscv that they're not for the RISC-V > tree. > > That said, it looks like I put the Kendryte stuff in there (so sorry if > I screwed anything up). I'm happy to take these via the RISC-V tree as > well, I'm assuming that means there should be a MAINTAINERS entry for > this new sub-directory so changes to it are less likely to get lost. > Sorry if I was confusing before, I guess I forgot about how this fits > together. > > Arnd: aside from the lack of a maintainer, these generally look fine to > me. LMK if you were expecting this kind of stuff to go through the > RISC-V tree. It probably helps avoid merge conflicts to go through the soc tree, as there are generally more changes for arm specific socs in there. However, we usually take pull requests from platform maintainers, not individual patches. For Microchip's ARM based platforms, those patches would go through the AT91/SAMA5 maintainers (added to Cc). You can ask them if they are willing to take future patches for the polarfire soc as well and forward them to soc@kernel.org along with the other stuff. > >> +int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, void *msg) > >> +{ > >> + int ret; > >> + > >> + mutex_lock_interruptible(&transaction_lock); When you do a mutex_lock_interruptible(), you have to check its return code and handle the interruption, usually by passing down -EINTR to the caller. > >> +struct mpfs_sys_controller * > >> +mpfs_sys_controller_get(struct device_node *mss_node) > >> +{ > >> + struct platform_device *pdev = of_find_device_by_node(mss_node); > >> + > >> + if (!pdev) > >> + return NULL; > >> + > >> + return platform_get_drvdata(pdev); > >> +} > >> +EXPORT_SYMBOL(mpfs_sys_controller_get); There should probably be a check in here to ensure that this is actually a system controller and it's bound do this driver, rather than returning a random device's driver data. It might also help to make this take a phandle instead of a device node for lookup, to spare the client the extra phandle to node conversion. Arnd _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv