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Wed, 31 Mar 2021 07:12:27 +0000 Received: from mout.kundenserver.de ([217.72.192.75]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lRV1b-005kKd-P5 for linux-riscv@lists.infradead.org; Wed, 31 Mar 2021 07:12:25 +0000 Received: from mail-ot1-f42.google.com ([209.85.210.42]) by mrelayeu.kundenserver.de (mreue107 [213.165.67.113]) with ESMTPSA (Nemesis) id 1MxEcg-1lpvf31gLY-00xeFv for ; Wed, 31 Mar 2021 09:12:21 +0200 Received: by mail-ot1-f42.google.com with SMTP id t23-20020a0568301e37b02901b65ab30024so18071296otr.4 for ; Wed, 31 Mar 2021 00:12:20 -0700 (PDT) X-Gm-Message-State: AOAM530QBBgBZrG7hBX8YUhvxqsvF3NPoQK90iYMeC21BCyTwr/X9Yn7 zUe9P/A0N9yThgLe2pjTHpqPrPoiK2K3xjKgI9I= X-Google-Smtp-Source: ABdhPJyDDdJN4bOkBUX/6z8TQTYJT7CTrMHBr52q+GIbBO0fps9qLwpUyqCwRyTxF2TfGzWqXN6oPJ/d9KksN2Qfcso= X-Received: by 2002:a9d:758b:: with SMTP id s11mr1622938otk.305.1617174739722; Wed, 31 Mar 2021 00:12:19 -0700 (PDT) MIME-Version: 1.0 References: <1616868399-82848-1-git-send-email-guoren@kernel.org> <1616868399-82848-4-git-send-email-guoren@kernel.org> In-Reply-To: From: Arnd Bergmann Date: Wed, 31 Mar 2021 09:12:05 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 3/4] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 To: Guo Ren Cc: Peter Zijlstra , linux-riscv , Linux Kernel Mailing List , linux-csky@vger.kernel.org, linux-arch , Guo Ren , Will Deacon , Ingo Molnar , Waiman Long , Anup Patel , Sebastian Andrzej Siewior X-Provags-ID: V03:K1:82DWx9iSOUZxIqETI3PBCOfoBE8fx2k0QZSrBpXzItTd+fJLISq rkjT1VhlT/aS+agv94c6mtJ+/suLtvTNsHwLaZsS/k1m6u6plJDZGaP5ndgJ4ea82HIhYcj MCQbwZZSPaV8hCo4h5znbBgCmwIEl6/Gb49eHCiNE1bkve6dTNAwfQZ1vO3iPg3wCMeTjB9 kt8gWsua6iYAatqIKqllg== X-UI-Out-Filterresults: notjunk:1;V03:K0:WRy0Ah4Ap6k=:Sp4g3chhYgg+O7ScpgNw+/ NORzq/hoiBUqdaXDO+gPLciCOJGArD9I2DdK+Da3bALDitCuImFZdyIPYXg6grtF0o2x5Gw5E USOhUjWObwzf4u/ObjNL5FZJxZRFkMBzACESyFBhRSdhs8vTIMN01uuWjJwtds/GhVdYnV8oC gOMbsA2GeW2iKkF6wTWpHDcuaVM5N509M9pMl0S0Yb7UOVuMM96ybftqqoBYgbxwbDptSb9Ag b/gtA1OQPo1soGFDbF4gARskPga0dzPEnO07qYdg5FvV6lyCbcbUCRWsxABo7KmR0/6eDgMyM A6VEKlosB0gtBuT+TahL7fOWY8qyeBXAkvBSDvfGWVv6YVk4W2i5s9Lrp3N8Q0AkgSESpJfUD qaayw+KpADOp0IOK08R/VB5osUNF+kqKVDG2IDhI3YW586Gw6FYLjxbdpFIx9pLFVX2DtgtYQ 4UX4BI+LNke6Rgd3mwpAELc4yEnNhydCkuoD2V7rrmvLW6pHqRLAgHuykDCWMzM+hK/Uu3n6z GfGKhNtcZeFuax8FqJfn9WRbF46vZ7zt0Be0A1Qy0znS7/QU7Fd7ubl4t8Fx5AJO7Bc3BZb+s BCZGisDA8EZHDi2rymmpnM/sl4i6mClZUY X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210331_081223_968467_41832C02 X-CRM114-Status: GOOD ( 19.43 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Mar 31, 2021 at 8:44 AM Guo Ren wrote: > On Wed, Mar 31, 2021 at 12:18 PM Guo Ren wrote: > > On Tue, Mar 30, 2021 at 3:12 PM Arnd Bergmann wrote: > > > On Tue, Mar 30, 2021 at 4:26 AM Guo Ren wrote: > > > As I understand, this example must not cause a deadlock on > > > a compliant hardware implementation when the underlying memory > > > has RsrvEventual behavior, but could deadlock in case of > > > RsrvNonEventual > > Thx for the nice explanation: > > - RsrvNonEventual - depends on software fall-back mechanisms, and > > just I'm worried about. > > - RsrvEventual - HW would provide the eventual success guarantee. > In riscv-spec 8.3 Eventual Success of Store-Conditional Instructions > > I found: > "As a consequence of the eventuality guarantee, if some harts in an > execution environment are > executing constrained LR/SC loops, and no other harts or devices in > the execution environment > execute an unconditional store or AMO to that reservation set, then at > least one hart will > eventually exit its constrained LR/SC loop. *** By contrast, if other > harts or devices continue to > write to that reservation set, it ***is not guaranteed*** that any > hart will exit its LR/SC loop.*** " > > Seems RsrvEventual couldn't solve the code's problem I've mentioned. Ok, got it. Arnd _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv