From: Anup Patel <apatel@ventanamicro.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Andrew Jones <ajones@ventanamicro.com>,
Atish Patra <atishp@atishpatra.org>,
Samuel Holland <samuel@sholland.org>,
Anup Patel <anup@brainfault.org>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/2] dt-bindings: riscv: Add optional DT property riscv,timer-can-wake-cpu
Date: Wed, 27 Jul 2022 17:51:05 +0530 [thread overview]
Message-ID: <CAK9=C2WjU+2cD7UZbja3TT++KCdRyWroT=50dw=fzi5mX30rcw@mail.gmail.com> (raw)
In-Reply-To: <372e37bf-ac90-c371-ad9e-b9c18e1cc059@linaro.org>
On Wed, Jul 27, 2022 at 5:37 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 27/07/2022 13:43, Anup Patel wrote:
> > We add an optional DT property riscv,timer-can-wake-cpu which if present
> > in CPU DT node then CPU timer is always powered-on and never loses context.
> >
> > Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> > ---
> > Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > index d632ac76532e..b60b64b4113a 100644
> > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > @@ -78,6 +78,12 @@ properties:
> > - rv64imac
> > - rv64imafdc
> >
> > + riscv,timer-can-wake-cpu:
> > + type: boolean
> > + description:
> > + If present, the timer interrupt can wake up the CPU from
> > + suspend/idle state.
>
> Isn't this a property of a timer, not CPU? IOW, your timer node should
> have "wakeup-source" property.
Historically (since the early days), we never had a timer node in the
RISC-V world.
>
> Now that's actual problem: why the RISC-V timer is bound to "riscv"
> compatible, not to dedicated timer node? How is it related to actual CPU
> (not SoC)?
The RISC-V timer is always present on all RISC-V platforms because
the "time" CSR is defined by RISC-V privileged specification. The method
to program per-CPU timer events in either using SBI call or Sstc CSRs.
Since, there is no dedicated timer node, we use CPU compatible string
for probing the per-CPU timer.
Regards,
Anup
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next prev parent reply other threads:[~2022-07-27 12:21 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-27 11:43 [PATCH v2 0/2] Improve CLOCK_EVT_FEAT_C3STOP feature setting Anup Patel
2022-07-27 11:43 ` [PATCH v2 1/2] dt-bindings: riscv: Add optional DT property riscv,timer-can-wake-cpu Anup Patel
2022-07-27 12:07 ` Krzysztof Kozlowski
2022-07-27 12:21 ` Anup Patel [this message]
2022-07-27 12:35 ` Krzysztof Kozlowski
2022-07-27 13:34 ` Anup Patel
2022-11-22 14:57 ` Conor Dooley
2022-11-23 5:43 ` Samuel Holland
2022-11-23 11:49 ` Conor Dooley
2022-11-23 13:46 ` Conor Dooley
2022-11-23 15:46 ` Anup Patel
2022-11-23 17:59 ` Conor Dooley
2022-07-27 12:45 ` Sudeep Holla
2022-07-27 13:19 ` Anup Patel
2022-07-27 13:45 ` Anup Patel
2022-07-27 15:26 ` Sudeep Holla
2022-07-27 12:18 ` Sudeep Holla
2022-07-27 12:29 ` Anup Patel
2022-07-27 11:43 ` [PATCH v2 2/2] clocksource: timer-riscv: Set CLOCK_EVT_FEAT_C3STOP based on DT property Anup Patel
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