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Tue, 14 Sep 2021 08:42:51 -0700 (PDT) MIME-Version: 1.0 References: <20210914121036.3975026-1-ardb@kernel.org> <20210914121036.3975026-2-ardb@kernel.org> In-Reply-To: From: Ard Biesheuvel Date: Tue, 14 Sep 2021 17:42:40 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RFC PATCH 1/8] arm64: add CPU field to struct thread_info To: Linus Torvalds Cc: Linux Kernel Mailing List , Keith Packard , Russell King , Catalin Marinas , Will Deacon , Michael Ellerman , Benjamin Herrenschmidt , Christophe Leroy , Paul Mackerras , Paul Walmsley , Palmer Dabbelt , Albert Ou , Heiko Carstens , Vasily Gorbik , Christian Borntraeger , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Peter Zijlstra , Kees Cook , Andy Lutomirski , Arnd Bergmann , Linux ARM , linuxppc-dev , linux-riscv , linux-s390 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210914_084303_205386_2E222E17 X-CRM114-Status: GOOD ( 14.60 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, 14 Sept 2021 at 17:41, Linus Torvalds wrote: > > On Tue, Sep 14, 2021 at 5:10 AM Ard Biesheuvel wrote: > > > > The CPU field will be moved back into thread_info even when > > THREAD_INFO_IN_TASK is enabled, so add it back to arm64's definition of > > struct thread_info. > > The series looks sane to me, but it strikes me that it's inconsistent > - here for arm64, you make it unconditional, but for the other > architectures you end up putting it inside a #ifdef CONFIG_SMP. > > Was there some reason for this odd behavior? > Yes. CONFIG_SMP is a 'def_bool y' on arm64. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv