From: Geert Uytterhoeven <geert@linux-m68k.org>
To: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Sagar Kadam <sagar.kadam@sifive.com>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
Phil Edworthy <phil.edworthy@renesas.com>,
Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH RFC 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC
Date: Wed, 25 May 2022 11:35:13 +0200 [thread overview]
Message-ID: <CAMuHMdVncBnD25RLLqL2qDFwboPSVvo5faJvamDxPH_wq9r22Q@mail.gmail.com> (raw)
In-Reply-To: <CA+V-a8ubrkDU2B=mJopzFrjhv1nVn5EXZmaprta0oj4p3J_N5Q@mail.gmail.com>
Hi Prabhakar,
On Wed, May 25, 2022 at 11:01 AM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Wed, May 25, 2022 at 9:01 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Tue, May 24, 2022 at 7:22 PM Lad Prabhakar
> > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The
> > > NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In
> > > case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt
> > > edge until the previous completion message has been received and
> > > NCEPLIC100 doesn't support pending interrupt counter, hence losing the
> > > interrupts if not acknowledged in time.
> > >
> > > So the workaround for edge-triggered interrupts to be handled correctly
> > > and without losing is that it needs to be acknowledged first and then
> > > handler must be run so that we don't miss on the next edge-triggered
> > > interrupt.
> > >
> > > This patch adds a new compatible string for Renesas RZ/Five SoC and adds
> > > support to change interrupt flow based on the interrupt type. It also
> > > implements irq_ack and irq_set_type callbacks.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Thanks for your patch!
> >
> > > --- a/drivers/irqchip/irq-sifive-plic.c
> > > +++ b/drivers/irqchip/irq-sifive-plic.c
> > > @@ -163,10 +166,31 @@ static int plic_set_affinity(struct irq_data *d,
> > > }
> > > #endif
> > >
> > > +static void plic_irq_ack(struct irq_data *d)
> > > +{
> > > + struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
> > > +
> >
> > No check for RZ/Five or irq type?
> That is because we set the handle_fasteoi_ack_irq() only in case of
> RZ/Five and it is already checked in set_type() callback.
>
> > .irq_ack() seems to be called for level interrupts, too
> > (from handle_level_irq() through mask_ack_irq()).
> >
> Right but we are using handle_fasteoi_irq() for level interrupt which
> doesn't call mask_ack_irq(). And I have confirmed by adding a print in
> ack callback and just enabling the serial (which has level
> interrupts).
But handle_fasteoi_irq() is configured only on RZ/Five below?
Which handler is used on non-RZ/Five?
I have to admit I'm not that deep into irq handling, and
adding a print indeed doesn't trigger on Starlight Beta.
> > > @@ -176,11 +200,37 @@ static void plic_irq_eoi(struct irq_data *d)
> > > }
> > > }
> > >
> > > +static int plic_irq_set_type(struct irq_data *d, unsigned int type)
> > > +{
> > > + struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
> > > +
> > > + if (handler->priv->of_data != RENESAS_R9A07G043_PLIC)
> > > + return 0;
> > > +
> > > + switch (type) {
> > > + case IRQ_TYPE_LEVEL_HIGH:
> > > + irq_set_handler_locked(d, handle_fasteoi_irq);
> > > + break;
> > > +
> > > + case IRQ_TYPE_EDGE_RISING:
> > > + irq_set_handler_locked(d, handle_fasteoi_ack_irq);
> > > + break;
> > > +
> > > + default:
> > > + return -EINVAL;
> > > + }
> > > +
> > > + return 0;
> > > +}
> > > +
> > > static struct irq_chip plic_chip = {
> > > .name = "SiFive PLIC",
> > > .irq_mask = plic_irq_mask,
> > > .irq_unmask = plic_irq_unmask,
> > > + .irq_ack = plic_irq_ack,
> >
> > This causes extra processing on non-affected PLICs.
> > Perhaps use a separate irq_chip instance?
> >
> I don't think so as the handle_fasteoi_ack_irq() is installed only in
> case of RZ/Five, so irq_ack() will not be called for non-affected
> PLIC's. Please correct me if I am wrong.
Hence I'll leave this to the irq maintainer...
> > > @@ -293,6 +356,9 @@ static int __init plic_init(struct device_node *node,
> > > if (!priv)
> > > return -ENOMEM;
> > >
> > > + if (of_device_is_compatible(node, "renesas-r9a07g043-plic"))
> > > + priv->of_data = RENESAS_R9A07G043_PLIC;
> > > +
> >
> > So perhaps instead just look at #interrupt-cells, and use the onecell
> > or twocell irq_chip/irq_domain_ops based on that?
> >
> But we do call plic_irq_domain_translate() in the alloc callback and
> don't have a node pointer in there to check the interrupt cell count.
> Or maybe we can store the interrupt cell count in priv and use it
> accordingly above?
That's a reasonable option.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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next prev parent reply other threads:[~2022-05-25 9:35 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-24 17:22 [PATCH RFC 0/2] Add PLIC support for Renesas RZ/Five SoC Lad Prabhakar
2022-05-24 17:22 ` [PATCH RFC 1/2] dt-bindings: interrupt-controller: sifive, plic: Document " Lad Prabhakar
2022-06-05 14:23 ` [PATCH RFC 1/2] dt-bindings: interrupt-controller: sifive,plic: " Rob Herring
2022-06-24 9:59 ` Lad, Prabhakar
2022-07-06 21:58 ` Rob Herring
2022-07-07 9:51 ` Marc Zyngier
2022-07-12 18:19 ` Rob Herring
2022-07-12 19:21 ` Marc Zyngier
2022-07-22 18:09 ` Rob Herring
2022-06-09 9:42 ` Geert Uytterhoeven
2022-06-24 10:01 ` Lad, Prabhakar
2022-05-24 17:22 ` [PATCH RFC 2/2] irqchip/sifive-plic: Add support for " Lad Prabhakar
2022-05-25 8:00 ` Geert Uytterhoeven
2022-05-25 9:00 ` Lad, Prabhakar
2022-05-25 9:35 ` Geert Uytterhoeven [this message]
2022-05-25 9:43 ` Lad, Prabhakar
2022-05-25 11:46 ` Geert Uytterhoeven
2022-05-27 11:05 ` Lad, Prabhakar
2022-06-06 15:41 ` Marc Zyngier
2022-06-07 12:41 ` Lad, Prabhakar
2022-06-08 10:27 ` Marc Zyngier
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