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[209.85.128.169]) by smtp.gmail.com with ESMTPSA id do39-20020a05620a2b2700b006cdd0939ffbsm6088969qkb.86.2022.11.27.02.03.08 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 27 Nov 2022 02:03:08 -0800 (PST) Received: by mail-yw1-f169.google.com with SMTP id 00721157ae682-3704852322fso79401237b3.8 for ; Sun, 27 Nov 2022 02:03:08 -0800 (PST) X-Received: by 2002:a5b:24b:0:b0:6ca:3b11:8d76 with SMTP id g11-20020a5b024b000000b006ca3b118d76mr25273660ybp.202.1669542919298; Sun, 27 Nov 2022 01:55:19 -0800 (PST) MIME-Version: 1.0 References: <20221124172207.153718-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221124172207.153718-8-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: Geert Uytterhoeven Date: Sun, 27 Nov 2022 10:55:07 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 7/7] soc: renesas: Add L2 cache management for RZ/Five SoC To: "Lad, Prabhakar" Cc: Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Geert Uytterhoeven , Magnus Damm , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Guo Ren , Jisheng Zhang , Atish Patra , Anup Patel , Andrew Jones , Nathan Chancellor , Philipp Tomsich , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Biju Das , Lad Prabhakar X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221127_020310_612536_52498FBA X-CRM114-Status: GOOD ( 43.94 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi Prabhakar, On Sat, Nov 26, 2022 at 10:10 PM Lad, Prabhakar wrote: > On Fri, Nov 25, 2022 at 7:43 PM Samuel Holland wrote: > > On 11/24/22 11:22, Prabhakar wrote: > > > From: Lad Prabhakar > > > > > > On the AX45MP core, cache coherency is a specification option so it may > > > not be supported. In this case DMA will fail. As a workaround, firstly we > > > allocate a global dma coherent pool from which DMA allocations are taken > > > and marked as non-cacheable + bufferable using the PMA region as specified > > > in the device tree. Synchronization callbacks are implemented to > > > synchronize when doing DMA transactions. > > > > > > The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA) > > > block that allows dynamic adjustment of memory attributes in the runtime. > > > It contains a configurable amount of PMA entries implemented as CSR > > > registers to control the attributes of memory locations in interest. > > > > > > Below are the memory attributes supported: > > > * Device, Non-bufferable > > > * Device, bufferable > > > * Memory, Non-cacheable, Non-bufferable > > > * Memory, Non-cacheable, Bufferable > > > * Memory, Write-back, No-allocate > > > * Memory, Write-back, Read-allocate > > > * Memory, Write-back, Write-allocate > > > * Memory, Write-back, Read and Write-allocate > > > > > > This patch adds support to configure the memory attributes of the memory > > > regions as passed from the l2 cache node and exposes the cache management > > > ops. > > > > Forgive my ignorance, but why do you need both a DMA pool and explicit > > cache maintenance? Wouldn't the purpose of marking a memory region as > > permanently non-cacheable be to avoid cache maintenance? And likewise, > > if you are doing cache maintenance anyway, why does it matter if/how the > > memory is cacheable? > > > "Memory, Non-cacheable, Bufferable" raises an AXI signal for > transactions hence needing SW implementation for cache maintenance. > > > > More info about PMA (section 10.3): > > > Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf > > > > > > Signed-off-by: Lad Prabhakar > > > +static int ax45mp_configure_pma_regions(struct device_node *np) > > > +{ > > > + const char *propname = "andestech,pma-regions"; > > > + u32 start, size, flags; > > > + unsigned int entry_id; > > > + unsigned int i; > > > + int count; > > > + int ret; > > > + > > > + count = of_property_count_elems_of_size(np, propname, sizeof(u32) * 3); > > > + if (count < 0) > > > + return count; > > > + > > > + if (count > AX45MP_MAX_PMA_REGIONS) > > > + return -EINVAL; > > > + > > > + for (i = 0, entry_id = 0 ; entry_id < count ; i += 3, entry_id++) { > > > + of_property_read_u32_index(np, propname, i, &start); > > > + of_property_read_u32_index(np, propname, i + 1, &size); > > > + of_property_read_u32_index(np, propname, i + 2, &flags); > > > + ret = ax45mp_sbi_set_pma(start, size, flags, entry_id); > > > + if (!ret) > > > + pr_err("Failed to setup PMA region 0x%x - 0x%x flags: 0x%x", > > > + start, start + size, flags); > > > + } > > > + > > > + return 0; > > > +} > > > > If firmware support is required to set up these PMA regions, why is > > Linux doing this at all? The firmware has access to the devicetree as > > well. It can set this up before entering S-mode, and then you don't need > > to expose this capability via an SBI extension. In fact, firmware could > > generate the reserved-memory node based on these regions at runtime (or > > vice versa). > > > That's a good point. I'll do some research on this and get back. > > Btw are there any existing examples where the firmware adds DT nodes? /memory, reserved-memory, optee on ARM, RPC status on R-Car Gen3/4, ... Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv