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[209.85.128.177]) by smtp.gmail.com with ESMTPSA id f39-20020a05622a1a2700b00342f05defd1sm2686496qtb.66.2022.08.19.01.04.55 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Aug 2022 01:04:57 -0700 (PDT) Received: by mail-yw1-f177.google.com with SMTP id 00721157ae682-33387bf0c4aso101896777b3.11 for ; Fri, 19 Aug 2022 01:04:55 -0700 (PDT) X-Received: by 2002:a0d:eb45:0:b0:333:f813:6c79 with SMTP id u66-20020a0deb45000000b00333f8136c79mr6390139ywe.384.1660896295663; Fri, 19 Aug 2022 01:04:55 -0700 (PDT) MIME-Version: 1.0 References: <20220815151451.23293-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20220815151451.23293-6-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20220815151451.23293-6-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Geert Uytterhoeven Date: Fri, 19 Aug 2022 10:04:43 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 5/8] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC To: Lad Prabhakar Cc: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Geert Uytterhoeven , Conor Dooley , Anup Patel , Linux-Renesas , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-riscv , Linux Kernel Mailing List , Prabhakar , Biju Das X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220819_010500_049034_95058765 X-CRM114-Status: GOOD ( 25.99 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi Prabhalar, On Mon, Aug 15, 2022 at 5:17 PM Lad Prabhakar wrote: > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP > Single). > > Below is the list of IP blocks added in the initial SoC DTSI which can be > used to boot via initramfs on RZ/Five SMARC EVK: > - AX45MP CPU > - CPG > - PINCTRL > - PLIC > - SCIF0 > - SYSC > > Signed-off-by: Lad Prabhakar Thanks for your patch! > --- /dev/null > +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi > @@ -0,0 +1,121 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +/* > + * Device Tree Source for the RZ/Five SoC My first thought was: This should be arch/riscv/boot/dts/renesas/r9a07g043f01.dtsi, including the common r9a07g043.dtsi, shared by arch/arm64/boot/dts/renesas/r9a07g043u11.dtsi. Then I realized this is harder than it sounds, due: > + soc: soc { > + compatible = "simple-bus"; > + interrupt-parent = <&plic>; vs. "interrupt-parent = <&plic>;" for r9a07g043u11, but mostly due to > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + scif0: serial@1004b800 { > + compatible = "renesas,scif-r9a07g043", > + "renesas,scif-r9a07g044"; > + reg = <0 0x1004b800 0 0x400>; > + interrupts = <412 IRQ_TYPE_LEVEL_HIGH>, > + <414 IRQ_TYPE_LEVEL_HIGH>, > + <415 IRQ_TYPE_LEVEL_HIGH>, > + <413 IRQ_TYPE_LEVEL_HIGH>, > + <416 IRQ_TYPE_LEVEL_HIGH>, > + <416 IRQ_TYPE_LEVEL_HIGH>; vs. "interrupts = ..." on r9a07g043u11. Interestingly, the actual hardware interrupt numbers are the same, but the GIC DT bindings abstracts the offset of 32 by using a second cell and GIC_SPI. Unfortunately this cannot be handled by some CPP magic, as dtc does not support arithmetic operations yet. I expect this or similar issues to pop up everywhere, when more RISCV-V SoCs will appear that share the non-CPU parts with ARM SoCs. Ignoring this issue, which we probably can solve only later: Reviewed-by: Geert Uytterhoeven Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv