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From: Zong Li <zong.li@sifive.com>
To: Anup Patel <anup@brainfault.org>
Cc: linux-riscv <linux-riscv@lists.infradead.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	"linux-kernel@vger.kernel.org List"
	<linux-kernel@vger.kernel.org>, Alan Kao <alankao@andestech.com>,
	Paul Walmsley <paul.walmsley@sifive.com>
Subject: Re: [RFC PATCH 0/6] Support raw event and DT for perf on RISC-V
Date: Mon, 29 Jun 2020 20:53:04 +0800
Message-ID: <CANXhq0o9BMe6G6kv-zO7OvLTfKsz-4XKsoZJe3nxvX9_6uunvw@mail.gmail.com> (raw)
In-Reply-To: <CAAhSdy0Ed8zQ5LVZva6p2TWqTOzrDRtL0JJkAdmpzWFhzJLUfg@mail.gmail.com>

On Mon, Jun 29, 2020 at 4:28 PM Anup Patel <anup@brainfault.org> wrote:
>
> On Mon, Jun 29, 2020 at 11:22 AM Zong Li <zong.li@sifive.com> wrote:
> >
> > On Mon, Jun 29, 2020 at 12:53 PM Anup Patel <anup@brainfault.org> wrote:
> > >
> > > On Mon, Jun 29, 2020 at 8:49 AM Zong Li <zong.li@sifive.com> wrote:
> > > >
> > > > This patch set adds raw event support on RISC-V. In addition, we
> > > > introduce the DT mechanism to make our perf more generic and common.
> > > >
> > > > Currently, we set the hardware events by writing the mhpmeventN CSRs, it
> > > > would raise an illegal instruction exception and trap into m-mode to
> > > > emulate event selector CSRs access. It doesn't make sense because we
> > > > shouldn't write the m-mode CSRs in s-mode. Ideally, we should set event
> > > > selector through standard SBI call or the shadow CSRs of s-mode. We have
> > > > prepared a proposal of a new SBI extension, called "PMU SBI extension",
> > > > but we also discussing the feasibility of accessing these PMU CSRs on
> > > > s-mode at the same time, such as delegation mechanism, so I was
> > > > wondering if we could use SBI calls first and make the PMU SBI extension
> > > > as legacy when s-mode access mechanism is accepted by Foundation? or
> > > > keep the current situation to see what would happen in the future.
> > > >
> > > > This patch set also introduces the DT mechanism, we don't want to add too
> > > > much platform-dependency code in perf like other architectures, so we
> > > > put the mapping of generic hardware events to DT, then we can easy to
> > > > transfer generic hardware events to vendor's own hardware events without
> > > > any platfrom-dependency stuff in our perf.
> > >
> > > Please re-write this series to have RISC-V PMU driver as a regular
> > > platform driver as drivers/perf/riscv_pmu.c.
> > >
> > > The PMU related sources will have to be removed from arch/riscv.
> > >
> > > Based on implementation of final drivers/perf/riscv_pmu.c we will
> > > come-up with drivers/perf/riscv_sbi_pmu.c driver for SBI perf counters.
> > >
> >
> > There are some different ways to implement perf, and current
> > implementation seems to be consensus when perf was introduced at the
> > beginning [0][1]. I don't persist to which one, I could change the
> > implementation as you mentioned if it is a new consensus one.
> >
> > [0] https://github.com/riscv/riscv-linux/pull/124#issuecomment-367563910
>
> I would not recommend taking the original RISC-V linux fork as reference.
>
> Rather we should study how things are done on other architectures.
>
> I really appreciate the attempt to make RISC-V PMU driver depend on DT
> but if we are going this route then we should maximize the use of Linux
> platform driver framework. In fact, whenever possible we should integrate
> RISC-V features as platform drivers under the drivers/ directory.
>

OK, I would change the implementation to platform driver if there is no
other voice.

> I thought about SBI PMU counters as well. In future, we can easily
> expose SBI PMU counters as RAW events in the same RISC-V PMU
> driver. The sbi_probe_extension() can be used in RISC-V PMU driver
> to check for SBI PMU counters so no special provisions needed in DT
> for SBI PMU counters.
>

I thought about probing raw events by SBI extension too, I'm interested if you
have more detail about this.

It seems to me that it is a little bit hard to return all events
through one SBI call,
so I thought we could map the generic hardware events and maintain their own
raw events by each platform in OpenSBI. But eventually, I thought the
DT mechanism
is more clear and easy than that. Let me know if you have any ideas about
probe function. Thanks.

> Also, the RISC-V PMU driver can be implemented such that it will
> work for RV32, RV64, NoMMU RV32, and NoMMU RV64.
>
> Regards,
> Anup
>
> > [1] https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/f19TmCNP6yA
> >
> > > Regards,
> > > Anup
> > >
> > > >
> > > > Zong Li (6):
> > > >   dt-bindings: riscv: Add YAML documentation for PMU
> > > >   riscv: dts: sifive: Add DT support for PMU
> > > >   riscv: add definition of hpmcounter CSRs
> > > >   riscv: perf: Add raw event support
> > > >   riscv: perf: introduce DT mechanism
> > > >   riscv: remove PMU menu of Kconfig
> > > >
> > > >  .../devicetree/bindings/riscv/pmu.yaml        |  59 +++
> > > >  arch/riscv/Kconfig                            |  13 -
> > > >  arch/riscv/boot/dts/sifive/fu540-c000.dtsi    |  13 +
> > > >  arch/riscv/include/asm/csr.h                  |  58 +++
> > > >  arch/riscv/include/asm/perf_event.h           | 100 ++--
> > > >  arch/riscv/kernel/Makefile                    |   2 +-
> > > >  arch/riscv/kernel/perf_event.c                | 471 +++++++++++-------
> > > >  7 files changed, 471 insertions(+), 245 deletions(-)
> > > >  create mode 100644 Documentation/devicetree/bindings/riscv/pmu.yaml
> > > >
> > > > --
> > > > 2.27.0
> > > >

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Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-29  3:19 Zong Li
2020-06-29  3:19 ` [RFC PATCH 1/6] dt-bindings: riscv: Add YAML documentation for PMU Zong Li
2020-06-29  4:09   ` Anup Patel
2020-06-29  4:28     ` Zong Li
2020-06-29  4:37       ` Anup Patel
2020-06-29  6:35         ` Zong Li
2020-06-29  8:31           ` Anup Patel
2020-07-01  3:22             ` Zong Li
2020-06-29  3:19 ` [RFC PATCH 2/6] riscv: dts: sifive: Add DT support " Zong Li
2020-06-29  3:19 ` [RFC PATCH 3/6] riscv: add definition of hpmcounter CSRs Zong Li
2020-06-29  3:19 ` [RFC PATCH 4/6] riscv: perf: Add raw event support Zong Li
2020-06-29  4:17   ` Anup Patel
2020-06-29  4:35     ` Zong Li
2020-06-29  4:40       ` Anup Patel
2020-06-29  3:19 ` [RFC PATCH 5/6] riscv: perf: introduce DT mechanism Zong Li
2020-06-29  4:36   ` Anup Patel
2020-06-29  6:26     ` Zong Li
2020-06-29  3:19 ` [RFC PATCH 6/6] riscv: remove PMU menu of Kconfig Zong Li
2020-06-29  4:52 ` [RFC PATCH 0/6] Support raw event and DT for perf on RISC-V Anup Patel
2020-06-29  5:52   ` Zong Li
2020-06-29  8:27     ` Anup Patel
2020-06-29 12:53       ` Zong Li [this message]
2020-06-29 13:23         ` Anup Patel
2020-06-30  6:37           ` Zong Li
2020-06-30  7:39             ` Anup Patel
2020-06-30  8:04               ` Zong Li
2020-06-30 10:18                 ` Anup Patel
2020-06-30 11:38                   ` Anup Patel
2020-06-30 18:57                     ` Atish Patra
2020-07-01  2:14                       ` Zong Li
2020-07-01 11:43                         ` Anup Patel
2020-07-01  2:11                     ` Zong Li
2020-07-01  1:55                   ` Zong Li
2020-07-01  0:51 ` Alan Kao
2020-07-01  1:02   ` Atish Patra
2020-07-01  2:45     ` Alan Kao
2020-07-01  3:15   ` Zong Li
2020-07-01  4:13   ` Anup Patel

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