From: Zong Li <zong.li@sifive.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv <linux-riscv@lists.infradead.org>,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 0/3] Get cache information from userland
Date: Mon, 27 Jul 2020 11:03:09 +0800 [thread overview]
Message-ID: <CANXhq0p7HO=zD7fDyz9O+TFzwFq2tqJva_V6RiFO6PExzuUq=g@mail.gmail.com> (raw)
In-Reply-To: <cover.1593766028.git.zong.li@sifive.com>
On Fri, Jul 3, 2020 at 4:57 PM Zong Li <zong.li@sifive.com> wrote:
>
> There are no standard CSR registers to provide cache information, the
> way for RISC-V is to get this information from DT. Currently, AT_L1I_X,
> AT_L1D_X and AT_L2_X are present in glibc header, and sysconf syscall
> could use them to get information of cache through AUX vector. We
> exploit 'struct cacheinfo' to obtain the information of cache, then we
> don't need additional variable or data structure to record it.
>
> We also need some works in glibc, but we have to support the function in
> kernel first by rule of glibc, then post the patch to glibc site.
>
> The result of 'getconf -a' as follows:
>
> LEVEL1_ICACHE_SIZE 32768
> LEVEL1_ICACHE_ASSOC 8
> LEVEL1_ICACHE_LINESIZE 64
> LEVEL1_DCACHE_SIZE 32768
> LEVEL1_DCACHE_ASSOC 8
> LEVEL1_DCACHE_LINESIZE 64
> LEVEL2_CACHE_SIZE 2097152
> LEVEL2_CACHE_ASSOC 32
> LEVEL2_CACHE_LINESIZE 64
>
> Zong Li (3):
> riscv: Set more data to cacheinfo
> riscv: Define AT_VECTOR_SIZE_ARCH for ARCH_DLINFO
> riscv: Add cache information in AUX vector
>
> arch/riscv/include/asm/cacheinfo.h | 14 +++++
> arch/riscv/include/asm/elf.h | 13 ++++
> arch/riscv/include/uapi/asm/auxvec.h | 24 ++++++++
> arch/riscv/kernel/cacheinfo.c | 92 +++++++++++++++++++++++-----
> 4 files changed, 127 insertions(+), 16 deletions(-)
> create mode 100644 arch/riscv/include/asm/cacheinfo.h
>
> --
> 2.27.0
>
ping
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2020-07-27 3:04 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-03 8:57 [PATCH 0/3] Get cache information from userland Zong Li
2020-07-03 8:57 ` [PATCH 1/3] riscv: Set more data to cacheinfo Zong Li
2020-08-20 20:44 ` Palmer Dabbelt
2020-07-03 8:57 ` [PATCH 2/3] riscv: Define AT_VECTOR_SIZE_ARCH for ARCH_DLINFO Zong Li
2020-08-20 20:44 ` Palmer Dabbelt
2020-07-03 8:57 ` [PATCH 3/3] riscv: Add cache information in AUX vector Zong Li
2020-08-20 20:44 ` Palmer Dabbelt
2020-07-27 3:03 ` Zong Li [this message]
2020-08-20 20:45 ` [PATCH 0/3] Get cache information from userland Palmer Dabbelt
2020-08-27 8:22 ` Zong Li
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CANXhq0p7HO=zD7fDyz9O+TFzwFq2tqJva_V6RiFO6PExzuUq=g@mail.gmail.com' \
--to=zong.li@sifive.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).