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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=LmoPe2SauK8cs9bRn6bTRLzxO3FPfMTTx1fSlCe95d8=; b=g+9CMTQCZEflHdr3lnm3UoHJyjJMSW/UbZuIFFbKTDnSWsOkZRik852QAxD5xLWerV 9iCrGmOT1DKEIbEPmuzwkJAOo/e0kJL1r88zQ8cIkTvEHxVUK5uwYn6AhajmeKUut7yq uPp6DyJIZAqAtlArf2ShtH4UV7mJArTBIvwFGV8ytar2ejft8Aoyv/yJSAbepI4M83Mh IAzXrnZ/TRdg2SR4TETrDseuNmqJ9wexyLH7msJprEROWe7U+U4j6+JB68j2am/2Bbb9 076Mjn58nHo0impoGYlDcKA3Xcw1xsVEVd3OHDWbdGEQPrsfB9DoG35sggvVlFOsx3Ih huvQ== X-Gm-Message-State: AOAM533GfRd546VcaQe1XWjtRLwNnvqfZgAPJs6rYv/8MYtdYdvN8a+Z qKneirAJQ5EijjDSRi7xe48tn6LDwFjPJqASfvoM+Q== X-Google-Smtp-Source: ABdhPJxuV9e/bdajpyOTCW3jUhfFs6GfvwaIjwyWuTWIcFYCNOoZ17sobH1l6CwPKbEcdycLek+MonZIX94hGVZ+Wls= X-Received: by 2002:a9d:186:: with SMTP id e6mr12147068ote.33.1593404899159; Sun, 28 Jun 2020 21:28:19 -0700 (PDT) MIME-Version: 1.0 References: <3de3a480517d167a3faae086aa8ab0c0c7141d99.1593397455.git.zong.li@sifive.com> In-Reply-To: From: Zong Li Date: Mon, 29 Jun 2020 12:28:08 +0800 Message-ID: Subject: Re: [RFC PATCH 1/6] dt-bindings: riscv: Add YAML documentation for PMU To: Anup Patel X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-riscv , Palmer Dabbelt , "linux-kernel@vger.kernel.org List" , Paul Walmsley Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Jun 29, 2020 at 12:09 PM Anup Patel wrote: > > On Mon, Jun 29, 2020 at 8:49 AM Zong Li wrote: > > > > Add device tree bindings for performance monitor unit. And it passes the > > dt_binding_check verification. > > > > Signed-off-by: Zong Li > > --- > > .../devicetree/bindings/riscv/pmu.yaml | 59 +++++++++++++++++++ > > 1 file changed, 59 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/riscv/pmu.yaml > > > > diff --git a/Documentation/devicetree/bindings/riscv/pmu.yaml b/Documentation/devicetree/bindings/riscv/pmu.yaml > > new file mode 100644 > > index 000000000000..f55ccbc6c685 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/riscv/pmu.yaml > > @@ -0,0 +1,59 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/riscv/pmu.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: RISC-V Performance Monitor Units > > + > > +maintainers: > > + - Zong Li > > + - Paul Walmsley > > + - Palmer Dabbelt > > + > > +properties: > > + compatible: > > + items: > > + - const: riscv,pmu > > + > > + riscv,width-base-cntr: > > + description: The width of cycle and instret CSRs. > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + > > + riscv,width-event-cntr: > > + description: The width of hpmcounter CSRs. > > + $ref: /schemas/types.yaml#/definitions/uint32 > > The terms "base" and "event" is confusing because > we only have counters with no interrupt associated with it. > > The RISC-V spec defines 3 counters and rest are all > implementation specific counters. As I know, there are 2 counters of spec definition: cycle and instret. What is the 3rd counter you mentioned? > > I suggest using the terms "spec counters" and "impl counters" > instead of "base counters" and "event counters". OK, they are good to me. Let me change it. > > Further, "riscv,width" properties are redundant because > RISC-V spec clearly tells that counters are 64bit for both > RV32 and RV64. > > > + > > + riscv,n-event-cntr: > > + description: The number of hpmcounter CSRs. > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + > > + riscv,hw-event-map: > > + description: The mapping of generic hardware events. Default is no mapping. > > + $ref: /schemas/types.yaml#/definitions/uint32-array > > + > > + riscv,hw-cache-event-map: > > + description: The mapping of generic hardware cache events. > > + Default is no mapping. > > + $ref: /schemas/types.yaml#/definitions/uint32-array > > + > > +required: > > + - compatible > > + - riscv,width-base-cntr > > + - riscv,width-event-cntr > > + - riscv,n-event-cntr > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + pmu { > > + compatible = "riscv,pmu"; > > + riscv,width-base-cntr = <64>; > > + riscv,width-event-cntr = <40>; > > + riscv,n-event-cntr = <2>; > > + riscv,hw-event-map = <0x0 0x0 0x1 0x1 0x3 0x0202 0x4 0x4000>; > > + riscv,hw-cache-event-map = <0x010201 0x0102 0x010204 0x0802>; > > + }; > > + > > +... > > -- > > 2.27.0 > > > > Regards, > Anup _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv