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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=etSf4B+EensBg61z3vriU5Um0L1QiBpVSWuAqrdE2/U=; b=JnSqNgqUAdEssrh1oZFUgJv31wGYnnjt4vYW9LI2y18GZkw+T7vBbRSySbLqO4d5gl Eo6qa3Ql6zu+h20KEcP4NG3V1VamfHrq+zPtmSKk8SXRfZ1+gqbI3CsiBaCO37qIKO12 PHtOCQdFga3I8BIwJyx0dzJouxpOaNjUIxEKA7GcbL+dRHkcif0Els7N/fV1yUQC6ObC hGGvPwzdLu3iC9pVnqO4Y0xETSI1ct6BKg8Xze6ds4q2Zym8P+iZ64UPi42kWCnuiMAT gQr0E4Xo/oMfgtbDwX6FYRjD1s/MRwrYRgwkZ0IAM0LILKFqfRediD8edfgAjQttKu+z /Y+g== X-Gm-Message-State: APjAAAXQ5niIEnyL+QJd0/HyShRsX02boLidfwF1HrTipxAOfwT4RFC+ KU9h9uwt6I3axdyXWcSDlVW/czpzVhNT+bKhk6rzZQ== X-Google-Smtp-Source: APXvYqwub+mpPiLYnwCae0Fe0SXyWet8+WfAkBCLua5YEmqOGz/7Vkh50hMcx/EgIuSfn7Qp77PKUsULuQkI9BA2YCo= X-Received: by 2002:aca:2210:: with SMTP id b16mr2373763oic.32.1580900882316; Wed, 05 Feb 2020 03:08:02 -0800 (PST) MIME-Version: 1.0 References: <20200204111947.52013-1-zong.li@sifive.com> In-Reply-To: From: Zong Li Date: Wed, 5 Feb 2020 19:07:52 +0800 Message-ID: Subject: Re: [PATCH] riscv: force hart_lottery to put in .sdata section To: Anup Patel Content-Type: text/plain; charset="UTF-8" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200205_030803_519630_D78F7C42 X-CRM114-Status: GOOD ( 16.03 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-riscv , Albert Ou , Palmer Dabbelt , "linux-kernel@vger.kernel.org List" , Paul Walmsley Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, Feb 4, 2020 at 7:40 PM Anup Patel wrote: > > On Tue, Feb 4, 2020 at 4:49 PM Zong Li wrote: > > > > In PIC code model, the zero initialized data always be put in .bss > > section, so when building kernel as PIE, the hart_lottery won't present > > in small data section, and it causes more than one harts to get the > > lottery, because the main hart clears the content of .bss section > > immediately after it getting the lottery. > > > > Signed-off-by: Zong Li > > --- > > arch/riscv/kernel/setup.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c > > index 22b671dbbcf1..45c63dc06360 100644 > > --- a/arch/riscv/kernel/setup.c > > +++ b/arch/riscv/kernel/setup.c > > @@ -40,7 +40,7 @@ struct screen_info screen_info = { > > #endif > > > > /* The lucky hart to first increment this variable will boot the other cores */ > > -atomic_t hart_lottery; > > +atomic_t hart_lottery __section(.sdata); > > unsigned long boot_cpu_hartid; > > > > void __init parse_dtb(void) > > -- > > 2.25.0 > > > > > > Looks good to me. Please ensure that it is tested with both > RV32 and RV64. > I had tested it on RV32 and RV64, it works on both. > Reviewed-by: Anup Patel > > Regards, > Anup