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bh=d0dV2iws6uddsenYWAYMkWA+zVZMQ5+yYDWKXhWbbSQ=; b=HzXnMKbNO1I1zAktjmW2YLI8nUFMmvdyJIt16B1dIPH6o8ZVziKFEge7d8Hgk2VI+0 jQ4rT8uRR7qgsJu636WP9WsQPKIl1eFjMCTpA3L9RmQaVZ1T6Z3NO4Ybb2nYyNuNtKa/ VJ7VCvSjzew3OxQJ4eQKHtncwpMzmGAGBx1e5dOnejrJgTuEFBn9idrXyWfFTn4CSynA 73GrsJPiT4UMb5zdB8Zikun5YbAxbt6DO8DAflrczTiXgYyFlhQp10U2YxCw4HZGnFlF xSdmnSz10qLf0WWJbtCn0VYkDnTrasUgiMJKmJQNair4wA9gw+3K+ahmN3E/8n2OPf3t Zsbg== X-Gm-Message-State: AOAM531691ag0s255QWFd4E32VdN6h/243yqasaVmm3JPpMlZ9LEJ3cE 512dnBRv+wCCED7MR3zcugaRF99umItQjNPxgcoT X-Google-Smtp-Source: ABdhPJwowXforkH2kxs2VccCNf7vTEQdsTB93/wdFK6X6NUSYQbseWUxeAD3SlVT3geAqA1PlMFz5w+a7ix4YVgalLE= X-Received: by 2002:a05:600c:2f88:: with SMTP id t8mr11403103wmn.186.1595653482851; Fri, 24 Jul 2020 22:04:42 -0700 (PDT) MIME-Version: 1.0 References: <20200724071822.126758-1-anup.patel@wdc.com> <20200724071822.126758-5-anup.patel@wdc.com> In-Reply-To: <20200724071822.126758-5-anup.patel@wdc.com> From: Atish Patra Date: Fri, 24 Jul 2020 22:04:31 -0700 Message-ID: Subject: Re: [PATCH v6 4/4] dt-bindings: timer: Add CLINT bindings To: Anup Patel X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200725_010445_932656_F3470CBB X-CRM114-Status: GOOD ( 18.53 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Damien Le Moal , Albert Ou , Emil Renner Berhing , Anup Patel , Daniel Lezcano , "linux-kernel@vger.kernel.org List" , Atish Patra , Rob Herring , Palmer Dabbelt , Paul Walmsley , Palmer Dabbelt , Alistair Francis , Thomas Gleixner , linux-riscv Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, Jul 24, 2020 at 12:19 AM Anup Patel wrote: > > We add DT bindings documentation for CLINT device. > > Signed-off-by: Anup Patel > Reviewed-by: Palmer Dabbelt > Tested-by: Emil Renner Berhing > --- > .../bindings/timer/sifive,clint.yaml | 60 +++++++++++++++++++ > 1 file changed, 60 insertions(+) > create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.yaml > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > new file mode 100644 > index 000000000000..2a0e9cd9fbcf > --- /dev/null > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > @@ -0,0 +1,60 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/timer/sifive,clint.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: SiFive Core Local Interruptor > + > +maintainers: > + - Palmer Dabbelt > + - Anup Patel > + > +description: > + SiFive (and other RISC-V) SOCs include an implementation of the SiFive > + Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor > + interrupts. It directly connects to the timer and inter-processor interrupt > + lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local > + interrupt controller is the parent interrupt controller for CLINT device. > + The clock frequency of CLINT is specified via "timebase-frequency" DT > + property of "/cpus" DT node. The "timebase-frequency" DT property is > + described in Documentation/devicetree/bindings/riscv/cpus.yaml > + > +properties: > + compatible: > + items: > + - const: sifive,fu540-c000-clint > + - const: sifive,clint0 > + > + description: > + Should be "sifive,-clint" and "sifive,clint". > + Supported compatible strings are - > + "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated > + onto the SiFive FU540 chip, and "sifive,clint0" for the SiFive > + CLINT v0 IP block with no chip integration tweaks. > + Please refer to sifive-blocks-ip-versioning.txt for details > + > + reg: > + maxItems: 1 > + > + interrupts-extended: > + minItems: 1 > + > +additionalProperties: false > + > +required: > + - compatible > + - reg > + - interrupts-extended > + > +examples: > + - | > + timer@2000000 { > + compatible = "sifive,fu540-c000-clint", "sifive,clint0"; > + interrupts-extended = <&cpu1intc 3 &cpu1intc 7 > + &cpu2intc 3 &cpu2intc 7 > + &cpu3intc 3 &cpu3intc 7 > + &cpu4intc 3 &cpu4intc 7>; > + reg = <0x2000000 0x10000>; > + }; > +... > -- > 2.25.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv Reviewed-by: Atish Patra -- Regards, Atish _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv