From: Atish Patra <atishp@atishpatra.org>
To: Yu Chien Peter Lin <peterlin@andestech.com>
Cc: mark.rutland@arm.com, irogers@google.com, heiko@sntech.de,
geert+renesas@glider.be, alexander.shishkin@linux.intel.com,
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wefu@redhat.com
Subject: Re: [PATCH v7 06/16] perf: RISC-V: Eliminate redundant interrupt enable/disable operations
Date: Fri, 12 Jan 2024 12:17:23 -0800 [thread overview]
Message-ID: <CAOnJCUJuDk6euX_XKiQ3H=TSGU02fgGgqSq-WycDwurq1XkDHw@mail.gmail.com> (raw)
In-Reply-To: <20240110073917.2398826-7-peterlin@andestech.com>
On Tue, Jan 9, 2024 at 11:40 PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> The interrupt enable/disable operations are already performed by the
> IRQ chip functions riscv_intc_irq_unmask()/riscv_intc_irq_mask() during
> enable_percpu_irq()/disable_percpu_irq(). It can be done only once.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> ---
> This patch allows us to drop unnecessary ALT_SBI_PMU_OVF_{DISABLE,ENABLE}
> in the initial PATCH3 [1].
>
> [1] https://patchwork.kernel.org/project/linux-riscv/patch/20230907021635.1002738-4-peterlin@andestech.com/
>
> Changes v1 -> v2:
> - New patch
> Changes v2 -> v3:
> - No change
> Changes v3 -> v4:
> - No change
> Changes v4 -> v5:
> - No change
> Changes v5 -> v6:
> - No change
> Changes v6 -> v7:
> - No change
> ---
> drivers/perf/riscv_pmu_sbi.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> index 16acd4dcdb96..2edbc37abadf 100644
> --- a/drivers/perf/riscv_pmu_sbi.c
> +++ b/drivers/perf/riscv_pmu_sbi.c
> @@ -781,7 +781,6 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node)
> if (riscv_pmu_use_irq) {
> cpu_hw_evt->irq = riscv_pmu_irq;
> csr_clear(CSR_IP, BIT(riscv_pmu_irq_num));
> - csr_set(CSR_IE, BIT(riscv_pmu_irq_num));
> enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE);
> }
>
> @@ -792,7 +791,6 @@ static int pmu_sbi_dying_cpu(unsigned int cpu, struct hlist_node *node)
> {
> if (riscv_pmu_use_irq) {
> disable_percpu_irq(riscv_pmu_irq);
> - csr_clear(CSR_IE, BIT(riscv_pmu_irq_num));
> }
>
> /* Disable all counters access for user mode now */
> --
> 2.34.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
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next prev parent reply other threads:[~2024-01-12 20:17 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-10 7:39 [PATCH v7 00/16] Support Andes PMU extension Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 01/16] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 02/16] irqchip/riscv-intc: Allow large non-standard interrupt number Yu Chien Peter Lin
2024-01-10 15:11 ` Anup Patel
2024-01-12 23:44 ` Atish Patra
2024-01-10 7:39 ` [PATCH v7 03/16] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Yu Chien Peter Lin
2024-01-10 15:12 ` Anup Patel
2024-01-12 23:43 ` Atish Patra
2024-01-10 7:39 ` [PATCH v7 04/16] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin
2024-01-12 23:50 ` Atish Patra
2024-01-13 0:19 ` Conor Dooley
2024-01-13 0:31 ` Atish Patra
2024-01-10 7:39 ` [PATCH v7 05/16] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 06/16] perf: RISC-V: Eliminate redundant interrupt enable/disable operations Yu Chien Peter Lin
2024-01-12 20:17 ` Atish Patra [this message]
2024-01-10 7:39 ` [PATCH v7 07/16] RISC-V: Move T-Head PMU to CPU feature alternative framework Yu Chien Peter Lin
2024-01-16 20:55 ` Atish Patra
2024-01-17 0:16 ` Conor Dooley
2024-01-17 8:58 ` Atish Patra
2024-01-17 9:17 ` Conor Dooley
2024-01-17 22:32 ` Atish Patra
2024-01-17 23:02 ` Conor Dooley
2024-01-17 23:10 ` Palmer Dabbelt
2024-01-22 8:48 ` Yu-Chien Peter Lin
2024-01-17 3:35 ` Anup Patel
2024-01-17 9:01 ` Atish Patra
2024-01-10 7:39 ` [PATCH v7 08/16] perf: RISC-V: Introduce Andes PMU for perf event sampling Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 09/16] dt-bindings: riscv: Add T-Head PMU extension description Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 10/16] dt-bindings: riscv: Add Andes " Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 11/16] riscv: dts: allwinner: Add T-Head PMU extension for sun20i-d1s Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 12/16] riscv: dts: sophgo: Add T-Head PMU extension for cv1800b Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 13/16] riscv: dts: sophgo: Add T-Head PMU extension for sg2042 Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 14/16] riscv: dts: thead: Add T-Head PMU extension for th1520 Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 15/16] riscv: dts: renesas: Add Andes PMU extension for r9a07g043f Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 16/16] riscv: andes: Support specifying symbolic firmware and hardware raw events Yu Chien Peter Lin
2024-01-13 0:04 ` Atish Patra
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