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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=m5YeNHvt0zcypFW4gVIjV1wgNVF4tJqWRF5UGFIAvn4=; b=XDWhE70fG7L2l0+F/hiozv8aDxBKAn0Cg+vGkUSdPZpcMNoXDZeB/xytk603UU++m0 t3pMVsLdC+1mKO6NdWU0a87yDKGzvHt+ITWPohH6LmvZfyNKZfQrlOlT/X0/s/JKhZ5s LxPMPooFJwQDAMP08bQSXA3D0OSfIc/raNqSRoVSQ7HeorH/lPNTTHZeEm+Mo6qzTwr7 LuabS+pOlg6RSi+OmWbUhm7v8OcNdiocE8JwFRh2OhTvJKYXrChojGJqE1b/AJtw5gxa fJCmfRRcphylJsrz7uIkBks/xi0bvHjSKnCSuI1iUyUYZyp2YpZqxSrmnz8RLqchVVEP aBVw== X-Gm-Message-State: APjAAAVDChzY8WY4CA5eD2FDunja3JfVxhja1bc0460cAokLjhAtgVli jFyfVBl8oC5ZSTcyQxkyz68Bo5grtvQ0gI39cGI= X-Google-Smtp-Source: APXvYqy5EvtGXAtcjqdJE/hoBljmEVSM5SUwDsN118mX/n4a0tm5BdRhBgPAlea1wtiaGUu9m/X/X7PPUt3c0jDbo1c= X-Received: by 2002:ac8:2af4:: with SMTP id c49mr5784353qta.83.1559257709549; Thu, 30 May 2019 16:08:29 -0700 (PDT) MIME-Version: 1.0 References: <20190530222922.4269-1-luke.r.nels@gmail.com> In-Reply-To: <20190530222922.4269-1-luke.r.nels@gmail.com> From: Song Liu Date: Thu, 30 May 2019 16:08:18 -0700 Message-ID: Subject: Re: [PATCH bpf v2] bpf, riscv: clear high 32 bits for ALU32 add/sub/neg/lsh/rsh/arsh To: Luke Nelson X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190530_160830_917894_2F6C25F9 X-CRM114-Status: GOOD ( 15.58 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Song Liu , Albert Ou , bpf , Daniel Borkmann , =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , Palmer Dabbelt , Alexei Starovoitov , open list , Networking , Yonghong Song , linux-riscv@lists.infradead.org, Martin KaFai Lau , Xi Wang Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Thu, May 30, 2019 at 3:30 PM Luke Nelson wrote: > > In BPF, 32-bit ALU operations should zero-extend their results into > the 64-bit registers. > > The current BPF JIT on RISC-V emits incorrect instructions that perform > sign extension only (e.g., addw, subw) on 32-bit add, sub, lsh, rsh, > arsh, and neg. This behavior diverges from the interpreter and JITs > for other architectures. > > This patch fixes the bugs by performing zero extension on the destination > register of 32-bit ALU operations. > > Fixes: 2353ecc6f91f ("bpf, riscv: add BPF JIT for RV64G") > Cc: Xi Wang > Signed-off-by: Luke Nelson Acked-by: Song Liu > --- > The original patch is > https://lkml.org/lkml/2019/5/30/1370 > > This version is rebased against the bpf tree. > --- > arch/riscv/net/bpf_jit_comp.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/arch/riscv/net/bpf_jit_comp.c b/arch/riscv/net/bpf_jit_comp.c > index e5c8d675bd6e..426d5c33ea90 100644 > --- a/arch/riscv/net/bpf_jit_comp.c > +++ b/arch/riscv/net/bpf_jit_comp.c > @@ -751,10 +751,14 @@ static int emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx, > case BPF_ALU | BPF_ADD | BPF_X: > case BPF_ALU64 | BPF_ADD | BPF_X: > emit(is64 ? rv_add(rd, rd, rs) : rv_addw(rd, rd, rs), ctx); > + if (!is64) > + emit_zext_32(rd, ctx); > break; > case BPF_ALU | BPF_SUB | BPF_X: > case BPF_ALU64 | BPF_SUB | BPF_X: > emit(is64 ? rv_sub(rd, rd, rs) : rv_subw(rd, rd, rs), ctx); > + if (!is64) > + emit_zext_32(rd, ctx); > break; > case BPF_ALU | BPF_AND | BPF_X: > case BPF_ALU64 | BPF_AND | BPF_X: > @@ -795,14 +799,20 @@ static int emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx, > case BPF_ALU | BPF_LSH | BPF_X: > case BPF_ALU64 | BPF_LSH | BPF_X: > emit(is64 ? rv_sll(rd, rd, rs) : rv_sllw(rd, rd, rs), ctx); > + if (!is64) > + emit_zext_32(rd, ctx); > break; > case BPF_ALU | BPF_RSH | BPF_X: > case BPF_ALU64 | BPF_RSH | BPF_X: > emit(is64 ? rv_srl(rd, rd, rs) : rv_srlw(rd, rd, rs), ctx); > + if (!is64) > + emit_zext_32(rd, ctx); > break; > case BPF_ALU | BPF_ARSH | BPF_X: > case BPF_ALU64 | BPF_ARSH | BPF_X: > emit(is64 ? rv_sra(rd, rd, rs) : rv_sraw(rd, rd, rs), ctx); > + if (!is64) > + emit_zext_32(rd, ctx); > break; > > /* dst = -dst */ > @@ -810,6 +820,8 @@ static int emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx, > case BPF_ALU64 | BPF_NEG: > emit(is64 ? rv_sub(rd, RV_REG_ZERO, rd) : > rv_subw(rd, RV_REG_ZERO, rd), ctx); > + if (!is64) > + emit_zext_32(rd, ctx); > break; > > /* dst = BSWAP##imm(dst) */ > @@ -964,14 +976,20 @@ static int emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx, > case BPF_ALU | BPF_LSH | BPF_K: > case BPF_ALU64 | BPF_LSH | BPF_K: > emit(is64 ? rv_slli(rd, rd, imm) : rv_slliw(rd, rd, imm), ctx); > + if (!is64) > + emit_zext_32(rd, ctx); > break; > case BPF_ALU | BPF_RSH | BPF_K: > case BPF_ALU64 | BPF_RSH | BPF_K: > emit(is64 ? rv_srli(rd, rd, imm) : rv_srliw(rd, rd, imm), ctx); > + if (!is64) > + emit_zext_32(rd, ctx); > break; > case BPF_ALU | BPF_ARSH | BPF_K: > case BPF_ALU64 | BPF_ARSH | BPF_K: > emit(is64 ? rv_srai(rd, rd, imm) : rv_sraiw(rd, rd, imm), ctx); > + if (!is64) > + emit_zext_32(rd, ctx); > break; > > /* JUMP off */ > -- > 2.19.1 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv