From: Yash Shah <yash.shah@sifive.com>
To: Marc Zyngier <maz@kernel.org>
Cc: "mark.rutland@arm.com" <mark.rutland@arm.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>,
"jason@lakedaemon.net" <jason@lakedaemon.net>,
"atish.patra@wdc.com" <atish.patra@wdc.com>,
Sachin Ghadi <sachin.ghadi@sifive.com>,
"linus.walleij@linaro.org" <linus.walleij@linaro.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"bgolaszewski@baylibre.com" <bgolaszewski@baylibre.com>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"palmer@dabbelt.com" <palmer@dabbelt.com>,
Sagar Kadam <sagar.kadam@sifive.com>,
"linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>,
"Paul Walmsley \( Sifive\)" <paul.walmsley@sifive.com>,
"tglx@linutronix.de" <tglx@linutronix.de>,
"bmeng.cn@gmail.com" <bmeng.cn@gmail.com>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>
Subject: RE: [PATCH 3/4] gpio: sifive: Add GPIO driver for SiFive SoCs
Date: Mon, 18 Nov 2019 07:50:48 +0000 [thread overview]
Message-ID: <CH2PR13MB3368302564103DC1EC8907D68C4D0@CH2PR13MB3368.namprd13.prod.outlook.com> (raw)
In-Reply-To: <d82620dd33bdd6bb4d34e49600a506d1@www.loen.fr>
> -----Original Message-----
> From: Marc Zyngier <maz@kernel.org>
> Sent: 12 November 2019 18:28
> To: Yash Shah <yash.shah@sifive.com>
> Cc: linus.walleij@linaro.org; bgolaszewski@baylibre.com;
> robh+dt@kernel.org; mark.rutland@arm.com; palmer@dabbelt.com; Paul
> Walmsley ( Sifive) <paul.walmsley@sifive.com>; aou@eecs.berkeley.edu;
> tglx@linutronix.de; jason@lakedaemon.net; bmeng.cn@gmail.com;
> atish.patra@wdc.com; Sagar Kadam <sagar.kadam@sifive.com>; linux-
> gpio@vger.kernel.org; devicetree@vger.kernel.org; linux-
> riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Sachin Ghadi
> <sachin.ghadi@sifive.com>
> Subject: Re: [PATCH 3/4] gpio: sifive: Add GPIO driver for SiFive SoCs
>
> On 2019-11-12 13:21, Yash Shah wrote:
> > Adds the GPIO driver for SiFive RISC-V SoCs.
> >
> > Signed-off-by: Wesley W. Terpstra <wesley@sifive.com>
> > [Atish: Various fixes and code cleanup]
> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > Signed-off-by: Yash Shah <yash.shah@sifive.com>
>
> [...]
>
> > +static int sifive_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
> > + unsigned int child,
> > + unsigned int child_type,
> > + unsigned int *parent,
> > + unsigned int *parent_type)
> > +{
> > + /* All these interrupts are level high in the CPU */
> > + *parent_type = IRQ_TYPE_LEVEL_HIGH;
>
> It is bizare that you enforce LEVEL_HIGH here, while setting it to NONE in the
> PLIC driver. These things should be consistent.
Will change this to IRQ_TYPE_NONE.
>
> > + *parent = child + 7;
>
> Irk, magic numbers...
This is the offset for GPIO IRQs. Will add a macro for this.
Thanks for your comments!
- Yash
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next prev parent reply other threads:[~2019-11-18 7:50 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-12 12:11 [PATCH 0/4] GPIO & Hierarchy IRQ support for HiFive Unleashed Yash Shah
2019-11-12 12:11 ` [PATCH 1/4] irqchip: sifive: Support hierarchy irq domain Yash Shah
2019-11-12 12:43 ` Marc Zyngier
2019-11-18 7:14 ` Yash Shah
2019-11-12 12:12 ` [PATCH 2/4] gpio: sifive: Add DT documentation for SiFive GPIO Yash Shah
2019-11-18 16:53 ` Rob Herring
2019-11-12 12:12 ` [PATCH 3/4] gpio: sifive: Add GPIO driver for SiFive SoCs Yash Shah
2019-11-12 12:58 ` Marc Zyngier
2019-11-18 7:50 ` Yash Shah [this message]
2019-11-13 13:10 ` Bartosz Golaszewski
2019-11-18 10:03 ` Yash Shah
2019-11-18 10:15 ` Bartosz Golaszewski
2019-11-19 15:02 ` Linus Walleij
2019-11-19 16:41 ` Bartosz Golaszewski
2019-11-22 12:28 ` Linus Walleij
2019-11-22 12:39 ` Bartosz Golaszewski
2019-11-25 4:54 ` Yash Shah
2019-11-12 12:12 ` [PATCH 4/4] riscv: dts: Add DT support for SiFive FU540 GPIO driver Yash Shah
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