From: Yash Shah <yash.shah@sifive.com>
To: Linus Walleij <linus.walleij@linaro.org>,
Bartosz Golaszewski <bgolaszewski@baylibre.com>
Cc: "mark.rutland@arm.com" <mark.rutland@arm.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>,
"jason@lakedaemon.net" <jason@lakedaemon.net>,
"linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>,
"maz@kernel.org" <maz@kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"atish.patra@wdc.com" <atish.patra@wdc.com>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"palmer@dabbelt.com" <palmer@dabbelt.com>,
Sagar Kadam <sagar.kadam@sifive.com>,
"Paul Walmsley \( Sifive\)" <paul.walmsley@sifive.com>,
"tglx@linutronix.de" <tglx@linutronix.de>,
"bmeng.cn@gmail.com" <bmeng.cn@gmail.com>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
Sachin Ghadi <sachin.ghadi@sifive.com>
Subject: RE: [PATCH 3/4] gpio: sifive: Add GPIO driver for SiFive SoCs
Date: Mon, 25 Nov 2019 04:54:40 +0000 [thread overview]
Message-ID: <CH2PR13MB3368B3660A55C509272CE1238C4A0@CH2PR13MB3368.namprd13.prod.outlook.com> (raw)
In-Reply-To: <CACRpkdaDmd+0809wmiNwSRbsdHaDNzpbOaxCcx6bEfYuyzPNQg@mail.gmail.com>
> -----Original Message-----
> From: Linus Walleij <linus.walleij@linaro.org>
> Sent: 22 November 2019 17:58
> To: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> Cc: Yash Shah <yash.shah@sifive.com>; robh+dt@kernel.org;
> mark.rutland@arm.com; palmer@dabbelt.com; Paul Walmsley ( Sifive)
> <paul.walmsley@sifive.com>; aou@eecs.berkeley.edu; tglx@linutronix.de;
> jason@lakedaemon.net; maz@kernel.org; bmeng.cn@gmail.com;
> atish.patra@wdc.com; Sagar Kadam <sagar.kadam@sifive.com>; linux-
> gpio@vger.kernel.org; devicetree@vger.kernel.org; linux-
> riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Sachin Ghadi
> <sachin.ghadi@sifive.com>
> Subject: Re: [PATCH 3/4] gpio: sifive: Add GPIO driver for SiFive SoCs
>
> On Tue, Nov 19, 2019 at 5:42 PM Bartosz Golaszewski
> <bgolaszewski@baylibre.com> wrote:
> > wt., 19 lis 2019 o 16:03 Linus Walleij <linus.walleij@linaro.org> napisał(a):
> > > On Mon, Nov 18, 2019 at 11:15 AM Bartosz Golaszewski
> > > <bgolaszewski@baylibre.com> wrote:
>
> > > > pon., 18 lis 2019 o 11:03 Yash Shah <yash.shah@sifive.com> napisał(a):
> > > Is it really so? The bgpio_lock does protect the registers used by
> > > regmap-mmio but unless the interrupt code is also using the same
> > > registers it is fine to have a different lock for those.
> > >
> > > Is the interrupt code really poking into the very same registers as
> > > passed to bgpio_init()?
> > >
> > > Of course it could be seen as a bit dirty to poke around in the same
> > > memory space with regmap and the bgpio_* accessors but in practice
> > > it's no problem if they never touch the same things.
> > >
> > > Yours,
> > > Linus Walleij
> >
> > I'm wondering if it won't cause any inconsistencies when for example
> > interrupts are being triggered on input lines while we're also reading
> > their values? Seems to me it's just more clear to use a single lock
> > for a register range. Most drivers using gpio-mmio do just that in
> > their irq-related routines.
>
> OK good point. Just one lock for the whole thing is likely more maintainable
> even if it works with two different locks.
>
> > Anyway: even without using bgpio_lock this code is inconsistent: if
> > we're using regmap for interrupt registers, we should either decide to
> > rely on locking provided by regmap or disable it and use a locally
> > defined lock.
>
> OK makes sense, let's say we use the bgpio_lock everywhere for this.
>
> Yash: are you OK with this? (Haven't read the new patch set yet, maybe it is
> already fixed...)
Yes, I am ok with this. I will be sending v3 soon with this change.
- Yash
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next prev parent reply other threads:[~2019-11-25 4:54 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-12 12:11 [PATCH 0/4] GPIO & Hierarchy IRQ support for HiFive Unleashed Yash Shah
2019-11-12 12:11 ` [PATCH 1/4] irqchip: sifive: Support hierarchy irq domain Yash Shah
2019-11-12 12:43 ` Marc Zyngier
2019-11-18 7:14 ` Yash Shah
2019-11-12 12:12 ` [PATCH 2/4] gpio: sifive: Add DT documentation for SiFive GPIO Yash Shah
2019-11-18 16:53 ` Rob Herring
2019-11-12 12:12 ` [PATCH 3/4] gpio: sifive: Add GPIO driver for SiFive SoCs Yash Shah
2019-11-12 12:58 ` Marc Zyngier
2019-11-18 7:50 ` Yash Shah
2019-11-13 13:10 ` Bartosz Golaszewski
2019-11-18 10:03 ` Yash Shah
2019-11-18 10:15 ` Bartosz Golaszewski
2019-11-19 15:02 ` Linus Walleij
2019-11-19 16:41 ` Bartosz Golaszewski
2019-11-22 12:28 ` Linus Walleij
2019-11-22 12:39 ` Bartosz Golaszewski
2019-11-25 4:54 ` Yash Shah [this message]
2019-11-12 12:12 ` [PATCH 4/4] riscv: dts: Add DT support for SiFive FU540 GPIO driver Yash Shah
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