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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: sifive.com X-MS-Exchange-CrossTenant-Network-Message-Id: d41a66f8-3fbf-43be-e724-08d7964a5f0f X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Jan 2020 03:57:25.7011 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 22f88e9d-ae0d-4ed9-b984-cdc9be1529f1 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: o+OP+VEZjDHzOQObiN8lFsh/85yxU+EZpa3jHPsN/MDMHkLlssqfPJF6xIrsti2c0HcDfWeqQLS+DYUIy1VGWA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR13MB3590 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200110_195731_354807_E39F1229 X-CRM114-Status: GOOD ( 17.48 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "aou@eecs.berkeley.edu" , "james.morse@arm.com" , "linux-kernel@vger.kernel.org" , "rrichter@marvell.com" , "tony.luck@intel.com" , "bp@alien8.de" , "palmer@dabbelt.com" , "linux-riscv@lists.infradead.org" , "mchehab@kernel.org" , "linux-edac@vger.kernel.org" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org > -----Original Message----- > From: Paul Walmsley > Sent: 11 January 2020 07:17 > To: Yash Shah > Cc: palmer@dabbelt.com; aou@eecs.berkeley.edu; bp@alien8.de; > mchehab@kernel.org; tony.luck@intel.com; james.morse@arm.com; > rrichter@marvell.com; linux-riscv@lists.infradead.org; linux- > kernel@vger.kernel.org; linux-edac@vger.kernel.org > Subject: Re: [PATCH] riscv: move sifive_l2_cache.h to include/soc >=20 > On Fri, 10 Jan 2020, Paul Walmsley wrote: >=20 > > On Tue, 7 Jan 2020, Yash Shah wrote: > > > > > The commit 9209fb51896f ("riscv: move sifive_l2_cache.c to > > > drivers/soc") moves the sifive L2 cache driver to driver/soc. It did > > > not move the header file along with the driver. Therefore this patch > > > moves the header file to driver/soc > > > > > > Signed-off-by: Yash Shah > > > > Thanks, queued for v5.5-rc. >=20 > By the way, I fixed the include guard also. The queued patch follows. Thanks, somehow I had overseen that. - Yash >=20 >=20 > - Paul >=20 > From: Yash Shah > Date: Tue, 7 Jan 2020 22:09:06 -0800 > Subject: [PATCH] riscv: move sifive_l2_cache.h to include/soc >=20 > The commit 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc") > moves the sifive L2 cache driver to driver/soc. It did not move the heade= r file > along with the driver. Therefore this patch moves the header file to > driver/soc >=20 > Signed-off-by: Yash Shah > Reviewed-by: Anup Patel > [paul.walmsley@sifive.com: updated to fix the include guard] > Fixes: 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc") > Signed-off-by: Paul Walmsley > --- > drivers/edac/sifive_edac.c | 2 +- > drivers/soc/sifive/sifive_l2_cache.c | 2 +- > .../include/asm =3D> include/soc/sifive}/sifive_l2_cache.h | 6 +++--- > 3 files changed, 5 insertions(+), 5 deletions(-) rename > {arch/riscv/include/asm =3D> include/soc/sifive}/sifive_l2_cache.h (72%) >=20 > diff --git a/drivers/edac/sifive_edac.c b/drivers/edac/sifive_edac.c inde= x > 413cdb4a591d..c0cc72a3b2be 100644 > --- a/drivers/edac/sifive_edac.c > +++ b/drivers/edac/sifive_edac.c > @@ -10,7 +10,7 @@ > #include > #include > #include "edac_module.h" > -#include > +#include >=20 > #define DRVNAME "sifive_edac" >=20 > diff --git a/drivers/soc/sifive/sifive_l2_cache.c > b/drivers/soc/sifive/sifive_l2_cache.c > index a9ffff3277c7..a5069394cd61 100644 > --- a/drivers/soc/sifive/sifive_l2_cache.c > +++ b/drivers/soc/sifive/sifive_l2_cache.c > @@ -9,7 +9,7 @@ > #include > #include > #include > -#include > +#include >=20 > #define SIFIVE_L2_DIRECCFIX_LOW 0x100 > #define SIFIVE_L2_DIRECCFIX_HIGH 0x104 > diff --git a/arch/riscv/include/asm/sifive_l2_cache.h > b/include/soc/sifive/sifive_l2_cache.h > similarity index 72% > rename from arch/riscv/include/asm/sifive_l2_cache.h > rename to include/soc/sifive/sifive_l2_cache.h > index 04f6748fc50b..92ade10ed67e 100644 > --- a/arch/riscv/include/asm/sifive_l2_cache.h > +++ b/include/soc/sifive/sifive_l2_cache.h > @@ -4,8 +4,8 @@ > * > */ >=20 > -#ifndef _ASM_RISCV_SIFIVE_L2_CACHE_H > -#define _ASM_RISCV_SIFIVE_L2_CACHE_H > +#ifndef __SOC_SIFIVE_L2_CACHE_H > +#define __SOC_SIFIVE_L2_CACHE_H >=20 > extern int register_sifive_l2_error_notifier(struct notifier_block *nb);= extern > int unregister_sifive_l2_error_notifier(struct notifier_block *nb); @@ -1= 3,4 > +13,4 @@ extern int unregister_sifive_l2_error_notifier(struct notifier_b= lock > *nb); #define SIFIVE_L2_ERR_TYPE_CE 0 #define SIFIVE_L2_ERR_TYPE_UE 1 >=20 > -#endif /* _ASM_RISCV_SIFIVE_L2_CACHE_H */ > +#endif /* __SOC_SIFIVE_L2_CACHE_H */ > -- > 2.25.0.rc2 >=20 >=20