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From: Yash Shah <yash.shah@sifive.com>
To: Palmer Dabbelt <palmerdabbelt@google.com>
Cc: "aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>,
	Sachin Ghadi <sachin.ghadi@sifive.com>,
	Greg KH <gregkh@linuxfoundation.org>,
	"anup@brainfault.org" <anup@brainfault.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"alexios.zavras@intel.com" <alexios.zavras@intel.com>,
	"Paul Walmsley \( Sifive\)" <paul.walmsley@sifive.com>,
	"tglx@linutronix.de" <tglx@linutronix.de>,
	"bp@suse.de" <bp@suse.de>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	"allison@lohutok.net" <allison@lohutok.net>
Subject: RE: [PATCH v4 2/2] riscv: Add support to determine no. of L2 cache way enabled
Date: Tue, 18 Feb 2020 06:25:27 +0000
Message-ID: <CH2PR13MB3368F10B94CA4FF8D569BD078C110@CH2PR13MB3368.namprd13.prod.outlook.com> (raw)
In-Reply-To: <mhng-4c96b04e-5adc-4b88-8b39-715cd765e6a5@palmerdabbelt-glaptop1>

> -----Original Message-----
> From: Palmer Dabbelt <palmerdabbelt@google.com>
> Sent: 07 February 2020 23:54
> To: Yash Shah <yash.shah@sifive.com>
> Cc: Paul Walmsley ( Sifive) <paul.walmsley@sifive.com>;
> aou@eecs.berkeley.edu; allison@lohutok.net; alexios.zavras@intel.com;
> Greg KH <gregkh@linuxfoundation.org>; tglx@linutronix.de; bp@suse.de;
> anup@brainfault.org; linux-riscv@lists.infradead.org; linux-
> kernel@vger.kernel.org; Sachin Ghadi <sachin.ghadi@sifive.com>; Yash Shah
> <yash.shah@sifive.com>
> Subject: Re: [PATCH v4 2/2] riscv: Add support to determine no. of L2 cache
> way enabled
> 
> On Thu, 16 Jan 2020 23:43:38 PST (-0800), yash.shah@sifive.com wrote:
> > In order to determine the number of L2 cache ways enabled at runtime,
> > implement a private attribute ("number_of_ways_enabled"). Reading this
> > attribute returns the number of enabled L2 cache ways at runtime.
> >
> > Using riscv_set_cacheinfo_ops() hook a custom function, that returns
> > this private attribute, to the generic ops structure which is used by
> > cache_get_priv_group() in cacheinfo framework.
> >
> > Signed-off-by: Yash Shah <yash.shah@sifive.com>
> > Reviewed-by: Anup Patel <anup@brainfault.org>
> > ---
> >  drivers/soc/sifive/sifive_l2_cache.c | 38
> > ++++++++++++++++++++++++++++++++++++
> >  1 file changed, 38 insertions(+)
> >
> > diff --git a/drivers/soc/sifive/sifive_l2_cache.c
> > b/drivers/soc/sifive/sifive_l2_cache.c
> > index a506939..3fb6404 100644
> > --- a/drivers/soc/sifive/sifive_l2_cache.c
> > +++ b/drivers/soc/sifive/sifive_l2_cache.c
> > @@ -9,6 +9,8 @@
> >  #include <linux/interrupt.h>
> >  #include <linux/of_irq.h>
> >  #include <linux/of_address.h>
> > +#include <linux/device.h>
> > +#include <asm/cacheinfo.h>
> >  #include <soc/sifive/sifive_l2_cache.h>
> >
> >  #define SIFIVE_L2_DIRECCFIX_LOW 0x100 @@ -31,6 +33,7 @@
> >
> >  static void __iomem *l2_base;
> >  static int g_irq[SIFIVE_L2_MAX_ECCINTR];
> > +static struct riscv_cacheinfo_ops l2_cache_ops;
> >
> >  enum {
> >  	DIR_CORR = 0,
> > @@ -107,6 +110,38 @@ int unregister_sifive_l2_error_notifier(struct
> > notifier_block *nb)  }
> > EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier);
> >
> > +static int l2_largest_wayenabled(void) {
> > +	return readl(l2_base + SIFIVE_L2_WAYENABLE); }
> 
> WayEnable is 8 bits.

Ok, will mask out and return the last 8 bits only

Thanks for your comment.

- Yash

      reply index

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-17  7:43 [PATCH v4 0/2] cacheinfo support to read no. of L2 cache ways enabled Yash Shah
2020-01-17  7:43 ` [PATCH v4 1/2] riscv: cacheinfo: Implement cache_get_priv_group with a generic ops structure Yash Shah
2020-01-17  7:43 ` [PATCH v4 2/2] riscv: Add support to determine no. of L2 cache way enabled Yash Shah
2020-02-07 18:24   ` Palmer Dabbelt
2020-02-18  6:25     ` Yash Shah [this message]

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