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* [PATCH] riscv: move flush_icache_{all,mm} code to proper location
@ 2019-03-06 17:00 Gary Guo
  2019-03-08 14:24 ` [PATCH] riscv: move flush_icache_{all, mm} " Christoph Hellwig
  2019-05-21 10:38 ` Andreas Schwab
  0 siblings, 2 replies; 5+ messages in thread
From: Gary Guo @ 2019-03-06 17:00 UTC (permalink / raw)
  To: linux-riscv

Currently, flush_icache_all is macro-expanded into a SBI call, yet no
asm/sbi.h is included in asm/cacheflush.h. This could be moved to
mm/cacheflush.c instead (SBI call will dominate performance-wise and there
is no worry to not have it inlined.

Currently, flush_icache_mm stays in kernel/smp.c, which looks like a hack
to prevent it from being compiled when CONFIG_SMP=n. It should also be in
mm/cacheflush.c.

Signed-off-by: Xuan Guo <gary@garyguo.net>
---
 arch/riscv/include/asm/cacheflush.h |  2 +-
 arch/riscv/kernel/smp.c             | 49 -----------------------
 arch/riscv/mm/cacheflush.c          | 61 +++++++++++++++++++++++++++++
 3 files changed, 62 insertions(+), 50 deletions(-)

diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h
index 8f13074413a7..1f4ba68ab9aa 100644
--- a/arch/riscv/include/asm/cacheflush.h
+++ b/arch/riscv/include/asm/cacheflush.h
@@ -47,7 +47,7 @@ static inline void flush_dcache_page(struct page *page)
 
 #else /* CONFIG_SMP */
 
-#define flush_icache_all() sbi_remote_fence_i(NULL)
+void flush_icache_all(void);
 void flush_icache_mm(struct mm_struct *mm, bool local);
 
 #endif /* CONFIG_SMP */
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
index 57b1383e5ef7..f066344aaf42 100644
--- a/arch/riscv/kernel/smp.c
+++ b/arch/riscv/kernel/smp.c
@@ -162,52 +162,3 @@ void smp_send_reschedule(int cpu)
 	send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
 }
 
-/*
- * Performs an icache flush for the given MM context.  RISC-V has no direct
- * mechanism for instruction cache shoot downs, so instead we send an IPI that
- * informs the remote harts they need to flush their local instruction caches.
- * To avoid pathologically slow behavior in a common case (a bunch of
- * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
- * IPIs for harts that are not currently executing a MM context and instead
- * schedule a deferred local instruction cache flush to be performed before
- * execution resumes on each hart.
- */
-void flush_icache_mm(struct mm_struct *mm, bool local)
-{
-	unsigned int cpu;
-	cpumask_t others, hmask, *mask;
-
-	preempt_disable();
-
-	/* Mark every hart's icache as needing a flush for this MM. */
-	mask = &mm->context.icache_stale_mask;
-	cpumask_setall(mask);
-	/* Flush this hart's I$ now, and mark it as flushed. */
-	cpu = smp_processor_id();
-	cpumask_clear_cpu(cpu, mask);
-	local_flush_icache_all();
-
-	/*
-	 * Flush the I$ of other harts concurrently executing, and mark them as
-	 * flushed.
-	 */
-	cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
-	local |= cpumask_empty(&others);
-	if (mm != current->active_mm || !local) {
-		cpumask_clear(&hmask);
-		riscv_cpuid_to_hartid_mask(&others, &hmask);
-		sbi_remote_fence_i(hmask.bits);
-	} else {
-		/*
-		 * It's assumed that at least one strongly ordered operation is
-		 * performed on this hart between setting a hart's cpumask bit
-		 * and scheduling this MM context on that hart.  Sending an SBI
-		 * remote message will do this, but in the case where no
-		 * messages are sent we still need to order this hart's writes
-		 * with flush_icache_deferred().
-		 */
-		smp_mb();
-	}
-
-	preempt_enable();
-}
diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
index 498c0a0814fe..497b7d07af0c 100644
--- a/arch/riscv/mm/cacheflush.c
+++ b/arch/riscv/mm/cacheflush.c
@@ -14,6 +14,67 @@
 #include <asm/pgtable.h>
 #include <asm/cacheflush.h>
 
+#ifdef CONFIG_SMP
+
+#include <asm/sbi.h>
+
+void flush_icache_all(void)
+{
+	sbi_remote_fence_i(NULL);
+}
+
+/*
+ * Performs an icache flush for the given MM context.  RISC-V has no direct
+ * mechanism for instruction cache shoot downs, so instead we send an IPI that
+ * informs the remote harts they need to flush their local instruction caches.
+ * To avoid pathologically slow behavior in a common case (a bunch of
+ * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
+ * IPIs for harts that are not currently executing a MM context and instead
+ * schedule a deferred local instruction cache flush to be performed before
+ * execution resumes on each hart.
+ */
+void flush_icache_mm(struct mm_struct *mm, bool local)
+{
+	unsigned int cpu;
+	cpumask_t others, hmask, *mask;
+
+	preempt_disable();
+
+	/* Mark every hart's icache as needing a flush for this MM. */
+	mask = &mm->context.icache_stale_mask;
+	cpumask_setall(mask);
+	/* Flush this hart's I$ now, and mark it as flushed. */
+	cpu = smp_processor_id();
+	cpumask_clear_cpu(cpu, mask);
+	local_flush_icache_all();
+
+	/*
+	 * Flush the I$ of other harts concurrently executing, and mark them as
+	 * flushed.
+	 */
+	cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
+	local |= cpumask_empty(&others);
+	if (mm != current->active_mm || !local) {
+		cpumask_clear(&hmask);
+		riscv_cpuid_to_hartid_mask(&others, &hmask);
+		sbi_remote_fence_i(hmask.bits);
+	} else {
+		/*
+		 * It's assumed that at least one strongly ordered operation is
+		 * performed on this hart between setting a hart's cpumask bit
+		 * and scheduling this MM context on that hart.  Sending an SBI
+		 * remote message will do this, but in the case where no
+		 * messages are sent we still need to order this hart's writes
+		 * with flush_icache_deferred().
+		 */
+		smp_mb();
+	}
+
+	preempt_enable();
+}
+
+#endif /* CONFIG_SMP */
+
 void flush_icache_pte(pte_t pte)
 {
 	struct page *page = pte_page(pte);
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH] riscv: move flush_icache_{all, mm} code to proper location
  2019-03-06 17:00 [PATCH] riscv: move flush_icache_{all,mm} code to proper location Gary Guo
@ 2019-03-08 14:24 ` " Christoph Hellwig
  2019-03-08 15:23   ` Gary Guo
  2019-05-21 10:38 ` Andreas Schwab
  1 sibling, 1 reply; 5+ messages in thread
From: Christoph Hellwig @ 2019-03-08 14:24 UTC (permalink / raw)
  To: Gary Guo; +Cc: linux-riscv

On Wed, Mar 06, 2019 at 05:00:21PM +0000, Gary Guo wrote:
> Currently, flush_icache_all is macro-expanded into a SBI call, yet no
> asm/sbi.h is included in asm/cacheflush.h. This could be moved to
> mm/cacheflush.c instead (SBI call will dominate performance-wise and there
> is no worry to not have it inlined.
> 
> Currently, flush_icache_mm stays in kernel/smp.c, which looks like a hack
> to prevent it from being compiled when CONFIG_SMP=n. It should also be in
> mm/cacheflush.c.

The non-SMP version of flush_icache_mm should also move to cacheflush.c.

Please make this flush_icache_mm one patch, and the a second one on top
of that that just removes flush_icache_all and open codes the two
users.

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^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH] riscv: move flush_icache_{all, mm} code to proper location
  2019-03-08 14:24 ` [PATCH] riscv: move flush_icache_{all, mm} " Christoph Hellwig
@ 2019-03-08 15:23   ` Gary Guo
  2019-03-08 16:28     ` Christoph Hellwig
  0 siblings, 1 reply; 5+ messages in thread
From: Gary Guo @ 2019-03-08 15:23 UTC (permalink / raw)
  To: Christoph Hellwig; +Cc: linux-riscv

Thanks for reply. I wonder what is the purpose for moving the non-SMP 
version? The non-SMP are just plain fence.i instructions that could just 
be inlined directly isn't it?

On 08/03/2019 14:24, Christoph Hellwig wrote:
> On Wed, Mar 06, 2019 at 05:00:21PM +0000, Gary Guo wrote:
>> Currently, flush_icache_all is macro-expanded into a SBI call, yet no
>> asm/sbi.h is included in asm/cacheflush.h. This could be moved to
>> mm/cacheflush.c instead (SBI call will dominate performance-wise and there
>> is no worry to not have it inlined.
>>
>> Currently, flush_icache_mm stays in kernel/smp.c, which looks like a hack
>> to prevent it from being compiled when CONFIG_SMP=n. It should also be in
>> mm/cacheflush.c.
> 
> The non-SMP version of flush_icache_mm should also move to cacheflush.c.
> 
> Please make this flush_icache_mm one patch, and the a second one on top
> of that that just removes flush_icache_all and open codes the two
> users.
> 
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^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH] riscv: move flush_icache_{all, mm} code to proper location
  2019-03-08 15:23   ` Gary Guo
@ 2019-03-08 16:28     ` Christoph Hellwig
  0 siblings, 0 replies; 5+ messages in thread
From: Christoph Hellwig @ 2019-03-08 16:28 UTC (permalink / raw)
  To: Gary Guo; +Cc: Christoph Hellwig, linux-riscv

On Fri, Mar 08, 2019 at 03:23:22PM +0000, Gary Guo wrote:
> Thanks for reply. I wonder what is the purpose for moving the non-SMP 
> version? The non-SMP are just plain fence.i instructions that could just 
> be inlined directly isn't it?

Sorry, I missed a few additional users, I'm fine with keeping it inline.

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^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH] riscv: move flush_icache_{all, mm} code to proper location
  2019-03-06 17:00 [PATCH] riscv: move flush_icache_{all,mm} code to proper location Gary Guo
  2019-03-08 14:24 ` [PATCH] riscv: move flush_icache_{all, mm} " Christoph Hellwig
@ 2019-05-21 10:38 ` Andreas Schwab
  1 sibling, 0 replies; 5+ messages in thread
From: Andreas Schwab @ 2019-05-21 10:38 UTC (permalink / raw)
  To: Gary Guo; +Cc: linux-riscv

On Mär 06 2019, Gary Guo <gary@garyguo.net> wrote:

> diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h
> index 8f13074413a7..1f4ba68ab9aa 100644
> --- a/arch/riscv/include/asm/cacheflush.h
> +++ b/arch/riscv/include/asm/cacheflush.h
> @@ -47,7 +47,7 @@ static inline void flush_dcache_page(struct page *page)
>  
>  #else /* CONFIG_SMP */
>  
> -#define flush_icache_all() sbi_remote_fence_i(NULL)
> +void flush_icache_all(void);
>  void flush_icache_mm(struct mm_struct *mm, bool local);

ERROR: "flush_icache_all" [drivers/misc/lkdtm/lkdtm.ko] undefined!

Andreas.

-- 
Andreas Schwab, SUSE Labs, schwab@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE  1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."

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^ permalink raw reply	[flat|nested] 5+ messages in thread

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Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-06 17:00 [PATCH] riscv: move flush_icache_{all,mm} code to proper location Gary Guo
2019-03-08 14:24 ` [PATCH] riscv: move flush_icache_{all, mm} " Christoph Hellwig
2019-03-08 15:23   ` Gary Guo
2019-03-08 16:28     ` Christoph Hellwig
2019-05-21 10:38 ` Andreas Schwab

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