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Thu, 30 May 2019 08:07:50 +0000 Received: from MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::98ab:5e60:9c5c:4e0e]) by MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::98ab:5e60:9c5c:4e0e%7]) with mapi id 15.20.1922.021; Thu, 30 May 2019 08:07:50 +0000 From: Anup Patel To: "xvisor-devel@googlegroups.com" , "linux-riscv@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "kvm@vger.kernel.org" , "opensbi@lists.infradead.org" Subject: RISC-V Hypervisors Thread-Topic: RISC-V Hypervisors Thread-Index: AdUWvgbyyaU5prZHR4mrJ6KOrYge6A== Date: Thu, 30 May 2019 08:07:50 +0000 Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-originating-ip: [103.20.29.89] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 3d2cc224-e414-460c-559a-08d6e4d5e909 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020); 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X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "krste@berkeley.edu" , Zvonimir Bandic , "waterman@eecs.berkeley.edu" , "palmer@sifive.com" , Damien Le Moal , Atish Patra , Alistair Francis , "pbonzini@redhat.com" , Ted Marena Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org Hi All, It's a great pleasure to inform everyone that we have RISC-V hypervisor extension available for QEMU and along with it we also have Xvisor (a baremetal type-1 hypervisor) working on QEMU with RISC-V hypervisor extension. Currently, we are able to boot two Linux RV64 Guests on Xvisor RV64. This will be very useful to RISC-V CPU designers in validating their implementation of RISC-V hypervisor extensions. The QEMU RISC-V hypervisor emulation is done by Alistair and is available in riscv-hyp-work.next branch at: https://github.com/alistair23/qemu.git. At the moment, QEMU RISC-V hypervisor emulation patches are on QEMU mailing list for review. (Refer, https://lists.gnu.org/archive/html/qemu-devel/2019-05/msg06064.html) The Xvisor RISC-V port is done by myself (Anup) and Atish. It can be found in master branch of Xvisor staging repo at: https://github.com/avpatel/xvisor-next.git. For more details on Xvisor, refer http://xhypervisor.org/ http://xhypervisor.org/index.php?page=news/20150427 The SBI runtime needs to support RISC-V hypervisor extensions. Particularly, we need to handle trap redirection, misaligned load/store emulation, and missing CSR emulation differently for HS-mode and VS-mode. We have extended OpenSBI to support RISC-V hypervisor extension and it is available in hyp_ext_changes_v1 branch at: https://github.com/riscv/opensbi.git We have made great progress in KVM RISC-V (type-2 hypervisor) as well. Currently, we are debugging KVM RISC-V and KVMTOOL RISC-V port on QEMU. You can expect RFC patches soon in June/July 2019. The KVM RISC-V can be found in riscv_kvm_v1 branch at: https://github.com/avpatel/linux.git The KVMTOOL RISC-V port can be found in riscv_v1 branch at: https://github.com/avpatel/kvmtool.git There is an early work on Xen RISC-V port which is avaliable in alistair/riscv-port branch at: https://github.com/alistair23/xen.git We will be showing a demo of QEMU+OpenSBI+Xvisor+Linux at up-coming RISC-V Zurich Workshop. (Refer, https://tmt.knect365.com/risc-v-workshop-zurich/) Stay tuned for more exciting updates on RISC-V hypervisors. Regards, Anup _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv