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X-IronPort-AV: E=Sophos;i="5.96,193,1665471600"; d="scan'208";a="188665806" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 25 Nov 2022 06:25:15 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 25 Nov 2022 06:25:13 -0700 Received: from wendy (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12 via Frontend Transport; Fri, 25 Nov 2022 06:25:10 -0700 Date: Fri, 25 Nov 2022 13:24:52 +0000 From: Conor Dooley To: "Lad, Prabhakar" CC: Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Geert Uytterhoeven , Magnus Damm , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Guo Ren , Jisheng Zhang , Atish Patra , Anup Patel , Andrew Jones , Nathan Chancellor , Philipp Tomsich , , , , , Biju Das , Lad Prabhakar Subject: Re: [PATCH v4 6/7] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Message-ID: References: <20221124172207.153718-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221124172207.153718-7-prabhakar.mahadev-lad.rj@bp.renesas.com> <70d1bfde-f57f-1741-08d3-23e362793595@linaro.org> <9b0f8312-2caa-b9f3-edf3-1b720532f559@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221125_052516_821188_219BDA01 X-CRM114-Status: GOOD ( 30.96 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, Nov 25, 2022 at 12:51:34PM +0000, Lad, Prabhakar wrote: > Hi Conor, > > On Fri, Nov 25, 2022 at 12:25 PM Conor Dooley > wrote: > > > > On Fri, Nov 25, 2022 at 01:12:18PM +0100, Krzysztof Kozlowski wrote: > > > On 25/11/2022 11:34, Lad, Prabhakar wrote: > > > >>> +/* Device, Non-bufferable */ > > > >>> +#define AX45MP_PMACFG_MTYP_DEV_NON_BUF (0 << 2) > > > >>> +/* Device, bufferable */ > > > >>> +#define AX45MP_PMACFG_MTYP_DEV_BUF (1 << 2) > > > >>> +/* Memory, Non-cacheable, Non-bufferable */ > > > >>> +#define AX45MP_PMACFG_MTYP_MEM_NON_CACHE_NON_BUF (2 << 2) > > > >>> +/* Memory, Non-cacheable, Bufferable */ > > > >>> +#define AX45MP_PMACFG_MTYP_MEM_NON_CACHE_BUF (3 << 2) > > > >> > > > >> What are all these? They don't look like flags, because 3 = 1 | 2... > > > >> they don't look like constants, because we do not use shifts in > > > >> constants. Are these some register values? I also do not see the header > > > >> being used in the code, so why having a bindings header if it is not > > > >> used (DTS is not usage...)? > > > >> > > > > These are register bit values for the MTYP[5:2] field. The DTS example > > > > in the binding doc (above) uses these macros. I haven't included the > > > > DTS/I patches with this patchset yet do think I should? > > > > > > Then why storing it as bindings? Bindings headers describe the interface > > > implemented by drivers and used by DTS, but this is not implemented by > > > drivers. > > > > IIUC, some of these properties are non-discoverable attributes of the > > cache controller. I see two things that could be done here that are > > "better" than #defining bits: > > - add an RZ/Five specific compatible and use match data to set the > > attributes which is only possible if the pma-regions are set on a > > per SoC basis > > - make pma-regions into a child node, in which andestech,non-cacheable > > andestech,non-bufferable etc are properties of the child node > > > For now the only way to get DMA working without IOCP is to have > AX45MP_PMACFG_MTYP_MEM_NON_CACHE_BUF. But for future purposes I have > introduced the other available flags. > > So maybe for now we could just have this flag > andestech,mem-non-cacheable-bufferable in the binding doc. > > cache-controller@2010000 { > reg = <0x13400000 0x100000>; > compatible = "andestech,ax45mp-cache", "cache"; > interrupts = <508 IRQ_TYPE_LEVEL_HIGH>; > cache-line-size = <64>; > cache-level = <2>; > cache-sets = <1024>; > cache-size = <262144>; > cache-unified; > andestech,pma-region@0x58000000 { > reg = <0x58000000 0x08000000>; > andestech,mem-non-cacheable-bufferable; Yah, that's about what I would expect - except splitting the properties up. I think split up makes more sense from a property description point of view, rather than needing some sort of oneOf: - non-cacheable-bufferable - cacheable-non-bufferable - non-cacheable-non-bufferable > }; > andestech,pma-region@0xdeadbeef { > reg = <0xdeadbeef 0x08000000>; > andestech,mem-non-cacheable-bufferable; > }; > .... > }; _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv