From: Peter Zijlstra <peterz@infradead.org>
To: Stafford Horne <shorne@gmail.com>
Cc: Boqun Feng <boqun.feng@gmail.com>,
guoren@kernel.org, linux-arch@vger.kernel.org,
linux-xtensa@linux-xtensa.org, Guo Ren <guoren@linux.alibaba.com>,
Arnd Bergmann <arnd@arndb.de>, Will Deacon <will@kernel.org>,
linux-kernel@vger.kernel.org, linux-csky@vger.kernel.org,
openrisc@lists.librecores.org, Anup Patel <anup@brainfault.org>,
sparclinux@vger.kernel.org, Waiman Long <longman@redhat.com>,
linux-riscv@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
Ingo Molnar <mingo@redhat.com>
Subject: Re: [OpenRISC] [PATCH v6 1/9] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
Date: Wed, 7 Apr 2021 11:47:49 +0200 [thread overview]
Message-ID: <YG1/xRgWlLHD4j/8@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <20210406235208.GG3288043@lianli.shorne-pla.net>
On Wed, Apr 07, 2021 at 08:52:08AM +0900, Stafford Horne wrote:
> Why doesn't RISC-V add the xchg16 emulation code similar to OpenRISC? For
> OpenRISC we added xchg16 and xchg8 emulation code to enable qspinlocks. So
> one thought is with CONFIG_ARCH_USE_QUEUED_SPINLOCKS_XCHG32=y, can we remove our
> xchg16/xchg8 emulation code?
CONFIG_ARCH_USE_QUEUED_SPINLOCKS_XCHG32 is guaranteed crap.
All the architectures that have wanted it are RISC style LL/SC archs,
and for them a cmpxchg loop is a daft thing to do, since it reduces the
chance of it behaving sanely.
Why would we provide something that's known to be suboptimal? If an
architecture chooses to not care about determinism and or fwd progress,
then that's their choice. But not one, I feel, we should encourage.
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next prev parent reply other threads:[~2021-04-07 9:48 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-31 14:30 [PATCH v6 0/9] riscv: Add qspinlock/qrwlock guoren
2021-03-31 14:30 ` [PATCH v6 1/9] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 guoren
2021-04-06 16:51 ` Boqun Feng
2021-04-06 23:52 ` [OpenRISC] " Stafford Horne
2021-04-07 9:47 ` Peter Zijlstra [this message]
2021-04-07 20:12 ` Stafford Horne
2021-04-08 19:00 ` Waiman Long
2021-03-31 14:30 ` [PATCH v6 2/9] riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock guoren
2021-03-31 14:30 ` [PATCH v6 3/9] riscv: locks: Introduce ticket-based spinlock implementation guoren
2021-04-05 5:54 ` Guo Ren
2021-04-11 16:02 ` Guo Ren
2021-04-11 16:51 ` Guo Ren
2021-03-31 14:30 ` [PATCH v6 4/9] csky: locks: Optimize coding convention guoren
2021-04-11 16:01 ` Guo Ren
2021-03-31 14:30 ` [PATCH v6 5/9] csky: Convert custom spinlock/rwlock to generic qspinlock/qrwlock guoren
2021-03-31 14:30 ` [PATCH v6 6/9] openrisc: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 guoren
2021-04-06 8:56 ` Stafford Horne
2021-03-31 14:30 ` [PATCH v6 7/9] sparc: " guoren
2021-03-31 14:30 ` [PATCH v6 8/9] xtensa: " guoren
2021-03-31 14:30 ` [PATCH v6 9/9] powerpc/qspinlock: " guoren
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