From: Jisheng Zhang <jszhang@kernel.org>
To: Atish Patra <atishp@atishpatra.org>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Anup Patel <anup@brainfault.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/2] riscv: introduce unified static key mechanism for ISA extensions
Date: Sun, 22 May 2022 22:56:25 +0800 [thread overview]
Message-ID: <YopPGSboPkZbbbGD@xhacker> (raw)
In-Reply-To: <CAOnJCU+aRoLRUjbum3o8N8J63vW+Y2974TjBueE__7PQAeJCQw@mail.gmail.com>
On Sun, May 22, 2022 at 12:33:12AM -0700, Atish Patra wrote:
> On Tue, May 17, 2022 at 11:53 AM Jisheng Zhang <jszhang@kernel.org> wrote:
> >
> > Currently, riscv has several extensions which may not be supported on
> > all riscv platforms, for example, FPU and so on. To support unified
> > kernel Image style, we need to check whether the feature is supported
>
> /s/suportted/supported
Thanks, will fix it in v2 soon.
>
> > or not. If the check sits at hot code path, then performance will be
> > impacted a lot. static key can be used to solve the issue. In the past
> > FPU support has been converted to use static key mechanism. I believe
> > we will have similar cases in the future.
> >
> > this patch tries to add an unified mechanism to use static keys for
> > some ISA extensions by implementing an array of default-false static keys
> > and enabling them when detected.
> >
> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > ---
> > arch/riscv/include/asm/hwcap.h | 40 ++++++++++++++++++++++++++++++++++
> > arch/riscv/kernel/cpufeature.c | 7 ++++++
> > 2 files changed, 47 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > index 0734e42f74f2..b0433d2b880d 100644
> > --- a/arch/riscv/include/asm/hwcap.h
> > +++ b/arch/riscv/include/asm/hwcap.h
> > @@ -12,6 +12,7 @@
> > #include <uapi/asm/hwcap.h>
> >
> > #ifndef __ASSEMBLY__
> > +#include <linux/jump_label.h>
> > /*
> > * This yields a mask that user programs can use to figure out what
> > * instruction set this cpu supports.
> > @@ -55,6 +56,16 @@ enum riscv_isa_ext_id {
> > RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
> > };
> >
> > +/*
> > + * This enum represents the logical ID for each RISC-V ISA extension static
> > + * keys. We can use static key to optimize code path if some ISA extensions
> > + * are available.
> > + */
> > +enum riscv_isa_ext_key {
> > + RISCV_ISA_EXT_KEY_FPU, /* For 'F' and 'D' */
> > + RISCV_ISA_EXT_KEY_MAX,
> > +};
> > +
> > struct riscv_isa_ext_data {
> > /* Name of the extension displayed to userspace via /proc/cpuinfo */
> > char uprop[RISCV_ISA_EXT_NAME_LEN_MAX];
> > @@ -62,6 +73,35 @@ struct riscv_isa_ext_data {
> > unsigned int isa_ext_id;
> > };
> >
> > +extern struct static_key_false riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_MAX];
> > +
> > +static __always_inline int riscv_isa_ext2key(int num)
> > +{
> > + switch (num) {
> > + case RISCV_ISA_EXT_f:
> > + return RISCV_ISA_EXT_KEY_FPU;
> > + case RISCV_ISA_EXT_d:
> > + return RISCV_ISA_EXT_KEY_FPU;
> > + default:
> > + return -EINVAL;
> > + }
> > +}
> > +
> > +/*
> > + * @num must be a compile-time constant.
> > + */
> > +static __always_inline bool riscv_isa_have_key_extension(int num)
> > +{
> > + if (RISCV_ISA_EXT_ID_MAX <= num)
> > + return false;
> > +
> > + num = riscv_isa_ext2key(num);
> > + if (RISCV_ISA_EXT_KEY_MAX <= num || num < 0)
> > + return false;
> > +
>
> Why do you need the additional check in the hot path ?
> riscv_isa_ext_keys array can be directly accessed at the caller
> instead of calling this function.
directly accessing the keys can make the code simpler, thanks for
the hint.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-05-22 15:05 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-17 18:44 [PATCH 0/2] introduce unified static key mechanism for ISA ext Jisheng Zhang
2022-05-17 18:44 ` [PATCH 1/2] riscv: introduce unified static key mechanism for ISA extensions Jisheng Zhang
2022-05-22 7:33 ` Atish Patra
2022-05-22 14:56 ` Jisheng Zhang [this message]
2022-05-17 18:44 ` [PATCH 2/2] riscv: switch has_fpu() to the unified static key mechanism Jisheng Zhang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=YopPGSboPkZbbbGD@xhacker \
--to=jszhang@kernel.org \
--cc=anup@brainfault.org \
--cc=aou@eecs.berkeley.edu \
--cc=atishp@atishpatra.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).