Linux-RISC-V Archive on lore.kernel.org
 help / Atom feed
* [PATCH v2 0/4] Timer code cleanup. 
@ 2018-12-13 23:14 Atish Patra
  2018-12-13 23:14 ` [PATCH v2 1/4] dt-bindings: Correct RISC-V's timebase-frequency Atish Patra
                   ` (3 more replies)
  0 siblings, 4 replies; 9+ messages in thread
From: Atish Patra @ 2018-12-13 23:14 UTC (permalink / raw)
  To: linux-kernel
  Cc: Mark Rutland, devicetree, Damien Le Moal, Albert Ou,
	Dmitriy Cherkasov, Anup Patel, Daniel Lezcano, Christoph Hellwig,
	Atish Patra, Rob Herring, Palmer Dabbelt, linux-riscv,
	Thomas Gleixner


This patch series provides an assorted timer cleanups in RISC-V.

Changes from v1->v2:

1. Updated commit text in 1/4.
2. Added a timebase check for each cpu.
3. Added a warning for invalid hartid 4/4.

Atish Patra (3):
RISC-V: Support per-hart timebase-frequency
RISC-V: Remove per cpu clocksource
RISC-V: Fix non-smp kernel boot on SMP systems

Palmer Dabbelt (1):
dt-bindings: Correct RISC-V's timebase-frequency

Documentation/devicetree/bindings/riscv/cpus.txt |  4 +-
arch/riscv/kernel/time.c                         |  9 +----
drivers/clocksource/riscv_timer.c                | 51 +++++++++++++++++++++---
3 files changed, 49 insertions(+), 15 deletions(-)

--
2.7.4


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v2 1/4] dt-bindings: Correct RISC-V's timebase-frequency
  2018-12-13 23:14 [PATCH v2 0/4] Timer code cleanup Atish Patra
@ 2018-12-13 23:14 ` Atish Patra
  2018-12-14  9:17   ` Daniel Lezcano
  2018-12-13 23:14 ` [PATCH v2 2/4] RISC-V: Support per-hart timebase-frequency Atish Patra
                   ` (2 subsequent siblings)
  3 siblings, 1 reply; 9+ messages in thread
From: Atish Patra @ 2018-12-13 23:14 UTC (permalink / raw)
  To: linux-kernel
  Cc: Mark Rutland, devicetree, Damien Le Moal, Palmer Dabbelt,
	Dmitriy Cherkasov, Anup Patel, Daniel Lezcano, Rob Herring,
	Christoph Hellwig, Atish Patra, Albert Ou, Thomas Gleixner,
	linux-riscv, Christoph Hellwig

From: Palmer Dabbelt <palmer@sifive.com>

In RISC-V systems, timebase-frequency is per cpu instead of one
instance for entire SOC as there is a individual timer per each CPU.
Fix the DT binding accordingly.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
[Atish: Update the commit text]
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/riscv/cpus.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt
index adf7b7af..b0b038d6 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.txt
+++ b/Documentation/devicetree/bindings/riscv/cpus.txt
@@ -93,9 +93,9 @@ Linux is allowed to run on.
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                timebase-frequency = <1000000>;
                 cpu@0 {
                         clock-frequency = <1600000000>;
+                        timebase-frequency = <1000000>;
                         compatible = "sifive,rocket0", "riscv";
                         device_type = "cpu";
                         i-cache-block-size = <64>;
@@ -113,6 +113,7 @@ Linux is allowed to run on.
                 };
                 cpu@1 {
                         clock-frequency = <1600000000>;
+                        timebase-frequency = <1000000>;
                         compatible = "sifive,rocket0", "riscv";
                         d-cache-block-size = <64>;
                         d-cache-sets = <64>;
@@ -145,6 +146,7 @@ Example: Spike ISA Simulator with 1 Hart
 This device tree matches the Spike ISA golden model as run with `spike -p1`.
 
         cpus {
+                timebase-frequency = <1000000>;
                 cpu@0 {
                         device_type = "cpu";
                         reg = <0x00000000>;
-- 
2.7.4


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v2 2/4] RISC-V: Support per-hart timebase-frequency
  2018-12-13 23:14 [PATCH v2 0/4] Timer code cleanup Atish Patra
  2018-12-13 23:14 ` [PATCH v2 1/4] dt-bindings: Correct RISC-V's timebase-frequency Atish Patra
@ 2018-12-13 23:14 ` Atish Patra
  2018-12-14  9:24   ` Daniel Lezcano
  2018-12-13 23:14 ` [PATCH v2 3/4] RISC-V: Remove per cpu clocksource Atish Patra
  2018-12-13 23:14 ` [PATCH v2 4/4] RISC-V: Fix non-smp kernel boot on SMP systems Atish Patra
  3 siblings, 1 reply; 9+ messages in thread
From: Atish Patra @ 2018-12-13 23:14 UTC (permalink / raw)
  To: linux-kernel
  Cc: Mark Rutland, devicetree, Damien Le Moal, Albert Ou,
	Dmitriy Cherkasov, Anup Patel, Daniel Lezcano, Christoph Hellwig,
	Atish Patra, Rob Herring, Palmer Dabbelt, linux-riscv,
	Thomas Gleixner

Follow the updated DT specs and read the timebase-frequency
from the boot cpu. Keep the old DT reading as well for backward
compatibility. This patch is rework of old patch from Palmer.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
 arch/riscv/kernel/time.c          |  9 +--------
 drivers/clocksource/riscv_timer.c | 31 +++++++++++++++++++++++++++++++
 2 files changed, 32 insertions(+), 8 deletions(-)

diff --git a/arch/riscv/kernel/time.c b/arch/riscv/kernel/time.c
index 1911c8f6..225fe743 100644
--- a/arch/riscv/kernel/time.c
+++ b/arch/riscv/kernel/time.c
@@ -20,14 +20,7 @@ unsigned long riscv_timebase;
 
 void __init time_init(void)
 {
-	struct device_node *cpu;
-	u32 prop;
-
-	cpu = of_find_node_by_path("/cpus");
-	if (!cpu || of_property_read_u32(cpu, "timebase-frequency", &prop))
-		panic(KERN_WARNING "RISC-V system with no 'timebase-frequency' in DTS\n");
-	riscv_timebase = prop;
+	timer_probe();
 
 	lpj_fine = riscv_timebase / HZ;
-	timer_probe();
 }
diff --git a/drivers/clocksource/riscv_timer.c b/drivers/clocksource/riscv_timer.c
index 084e97dc..75262409 100644
--- a/drivers/clocksource/riscv_timer.c
+++ b/drivers/clocksource/riscv_timer.c
@@ -83,6 +83,35 @@ void riscv_timer_interrupt(void)
 	evdev->event_handler(evdev);
 }
 
+static void __init riscv_timebase_frequency(struct device_node *node,
+					    int hartid)
+{
+	u32 timebase;
+
+	if (!of_property_read_u32(node, "timebase-frequency", &timebase))
+		goto check;
+
+	/*
+	 * As per the DT specification, timebase-frequency should be present
+	 * under individual cpu node. Unfortunately, there are already available
+	 * HiFive Unleashed devices where the timebase-frequency entry is under
+	 * CPUs. check under parent "cpus" node to cover those devices.
+	 */
+	if (!of_property_read_u32(node->parent, "timebase-frequency",
+				  &timebase))
+		goto check;
+
+	panic("RISC-V system with no timebase-frequency in DTS for hart [%d]\n",
+	      hartid);
+
+check:
+	/* RISC-V ISA specification mandates that every cpu has a timer */
+	if (!riscv_timebase)
+		riscv_timebase = timebase;
+	else if (riscv_timebase && riscv_timebase != timebase)
+		pr_warn("RISC-V system with different timebase-frequency\n");
+}
+
 static int __init riscv_timer_init_dt(struct device_node *n)
 {
 	int cpuid, hartid, error;
@@ -90,10 +119,12 @@ static int __init riscv_timer_init_dt(struct device_node *n)
 
 	hartid = riscv_of_processor_hartid(n);
 	cpuid = riscv_hartid_to_cpuid(hartid);
+	riscv_timebase_frequency(n, hartid);
 
 	if (cpuid != smp_processor_id())
 		return 0;
 
+	/* This should be called only for boot cpu */
 	cs = per_cpu_ptr(&riscv_clocksource, cpuid);
 	clocksource_register_hz(cs, riscv_timebase);
 
-- 
2.7.4


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v2 3/4] RISC-V: Remove per cpu clocksource
  2018-12-13 23:14 [PATCH v2 0/4] Timer code cleanup Atish Patra
  2018-12-13 23:14 ` [PATCH v2 1/4] dt-bindings: Correct RISC-V's timebase-frequency Atish Patra
  2018-12-13 23:14 ` [PATCH v2 2/4] RISC-V: Support per-hart timebase-frequency Atish Patra
@ 2018-12-13 23:14 ` Atish Patra
  2018-12-13 23:14 ` [PATCH v2 4/4] RISC-V: Fix non-smp kernel boot on SMP systems Atish Patra
  3 siblings, 0 replies; 9+ messages in thread
From: Atish Patra @ 2018-12-13 23:14 UTC (permalink / raw)
  To: linux-kernel
  Cc: Mark Rutland, devicetree, Damien Le Moal, Albert Ou,
	Dmitriy Cherkasov, Anup Patel, Daniel Lezcano, Christoph Hellwig,
	Atish Patra, Rob Herring, Palmer Dabbelt, linux-riscv,
	Thomas Gleixner

There is only one clocksource in RISC-V. The boot cpu initializes
that clocksource. No need to keep a percpu data structure.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
---
 drivers/clocksource/riscv_timer.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/clocksource/riscv_timer.c b/drivers/clocksource/riscv_timer.c
index 75262409..c9e65086 100644
--- a/drivers/clocksource/riscv_timer.c
+++ b/drivers/clocksource/riscv_timer.c
@@ -49,7 +49,7 @@ static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs)
 	return get_cycles64();
 }
 
-static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = {
+static struct clocksource riscv_clocksource = {
 	.name		= "riscv_clocksource",
 	.rating		= 300,
 	.mask		= CLOCKSOURCE_MASK(BITS_PER_LONG),
@@ -115,7 +115,6 @@ static void __init riscv_timebase_frequency(struct device_node *node,
 static int __init riscv_timer_init_dt(struct device_node *n)
 {
 	int cpuid, hartid, error;
-	struct clocksource *cs;
 
 	hartid = riscv_of_processor_hartid(n);
 	cpuid = riscv_hartid_to_cpuid(hartid);
@@ -125,8 +124,7 @@ static int __init riscv_timer_init_dt(struct device_node *n)
 		return 0;
 
 	/* This should be called only for boot cpu */
-	cs = per_cpu_ptr(&riscv_clocksource, cpuid);
-	clocksource_register_hz(cs, riscv_timebase);
+	clocksource_register_hz(&riscv_clocksource, riscv_timebase);
 
 	error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
 			 "clockevents/riscv/timer:starting",
-- 
2.7.4


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v2 4/4] RISC-V: Fix non-smp kernel boot on SMP systems
  2018-12-13 23:14 [PATCH v2 0/4] Timer code cleanup Atish Patra
                   ` (2 preceding siblings ...)
  2018-12-13 23:14 ` [PATCH v2 3/4] RISC-V: Remove per cpu clocksource Atish Patra
@ 2018-12-13 23:14 ` Atish Patra
  3 siblings, 0 replies; 9+ messages in thread
From: Atish Patra @ 2018-12-13 23:14 UTC (permalink / raw)
  To: linux-kernel
  Cc: Mark Rutland, devicetree, Damien Le Moal, Albert Ou,
	Dmitriy Cherkasov, Anup Patel, Daniel Lezcano, Christoph Hellwig,
	Atish Patra, Rob Herring, Palmer Dabbelt, linux-riscv,
	Thomas Gleixner

Currently, clocksource registration happens for an invalid cpu
for non-smp kernels. This lead to kernel panic as cpu hotplug
registration will fail for those cpus.

Do not proceed if hartid is invalid. Take this opprtunity to
print appropriate error strings for different failure cases.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
 drivers/clocksource/riscv_timer.c | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/clocksource/riscv_timer.c b/drivers/clocksource/riscv_timer.c
index c9e65086..c1e1260e 100644
--- a/drivers/clocksource/riscv_timer.c
+++ b/drivers/clocksource/riscv_timer.c
@@ -117,6 +117,11 @@ static int __init riscv_timer_init_dt(struct device_node *n)
 	int cpuid, hartid, error;
 
 	hartid = riscv_of_processor_hartid(n);
+	if (hartid < 0) {
+		pr_warn("Not valid hartid for node [%pOF] error = [%d]\n",
+			n, hartid);
+		return hartid;
+	}
 	cpuid = riscv_hartid_to_cpuid(hartid);
 	riscv_timebase_frequency(n, hartid);
 
@@ -124,14 +129,19 @@ static int __init riscv_timer_init_dt(struct device_node *n)
 		return 0;
 
 	/* This should be called only for boot cpu */
-	clocksource_register_hz(&riscv_clocksource, riscv_timebase);
+	error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
 
+	if (error) {
+		pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
+		       error, cpuid);
+		return error;
+	}
 	error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
 			 "clockevents/riscv/timer:starting",
 			 riscv_timer_starting_cpu, riscv_timer_dying_cpu);
 	if (error)
-		pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
-		       error, cpuid);
+		pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
+		       error);
 	return error;
 }
 
-- 
2.7.4


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH v2 1/4] dt-bindings: Correct RISC-V's timebase-frequency
  2018-12-13 23:14 ` [PATCH v2 1/4] dt-bindings: Correct RISC-V's timebase-frequency Atish Patra
@ 2018-12-14  9:17   ` Daniel Lezcano
  2019-01-04  0:36     ` Palmer Dabbelt
  0 siblings, 1 reply; 9+ messages in thread
From: Daniel Lezcano @ 2018-12-14  9:17 UTC (permalink / raw)
  To: Atish Patra, linux-kernel
  Cc: Mark Rutland, devicetree, Damien Le Moal, Albert Ou,
	Dmitriy Cherkasov, Anup Patel, Palmer Dabbelt, Christoph Hellwig,
	Rob Herring, Thomas Gleixner, linux-riscv, Christoph Hellwig

On 14/12/2018 00:14, Atish Patra wrote:
> From: Palmer Dabbelt <palmer@sifive.com>
> 
> In RISC-V systems, timebase-frequency is per cpu instead of one
> instance for entire SOC as there is a individual timer per each CPU.
> Fix the DT binding accordingly.

Why not use a fixed-clock instead of this timebase property which forces
to declare a global variable to be exported from arch/riscv to
drivers/clocksource ?

In addition, please add the 'Fixes' tag

> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> [Atish: Update the commit text]
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
>  Documentation/devicetree/bindings/riscv/cpus.txt | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt
> index adf7b7af..b0b038d6 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.txt
> +++ b/Documentation/devicetree/bindings/riscv/cpus.txt
> @@ -93,9 +93,9 @@ Linux is allowed to run on.
>          cpus {
>                  #address-cells = <1>;
>                  #size-cells = <0>;
> -                timebase-frequency = <1000000>;
>                  cpu@0 {
>                          clock-frequency = <1600000000>;
> +                        timebase-frequency = <1000000>;
>                          compatible = "sifive,rocket0", "riscv";
>                          device_type = "cpu";
>                          i-cache-block-size = <64>;
> @@ -113,6 +113,7 @@ Linux is allowed to run on.
>                  };
>                  cpu@1 {
>                          clock-frequency = <1600000000>;
> +                        timebase-frequency = <1000000>;
>                          compatible = "sifive,rocket0", "riscv";
>                          d-cache-block-size = <64>;
>                          d-cache-sets = <64>;
> @@ -145,6 +146,7 @@ Example: Spike ISA Simulator with 1 Hart
>  This device tree matches the Spike ISA golden model as run with `spike -p1`.
>  
>          cpus {
> +                timebase-frequency = <1000000>;
>                  cpu@0 {
>                          device_type = "cpu";
>                          reg = <0x00000000>;





-- 
 <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH v2 2/4] RISC-V: Support per-hart timebase-frequency
  2018-12-13 23:14 ` [PATCH v2 2/4] RISC-V: Support per-hart timebase-frequency Atish Patra
@ 2018-12-14  9:24   ` Daniel Lezcano
  0 siblings, 0 replies; 9+ messages in thread
From: Daniel Lezcano @ 2018-12-14  9:24 UTC (permalink / raw)
  To: Atish Patra, linux-kernel
  Cc: Mark Rutland, devicetree, Damien Le Moal, Albert Ou,
	Dmitriy Cherkasov, Anup Patel, Palmer Dabbelt, Christoph Hellwig,
	Rob Herring, linux-riscv, Thomas Gleixner

On 14/12/2018 00:14, Atish Patra wrote:
> Follow the updated DT specs and read the timebase-frequency
> from the boot cpu. Keep the old DT reading as well for backward
> compatibility. This patch is rework of old patch from Palmer.
> 
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
>  arch/riscv/kernel/time.c          |  9 +--------
>  drivers/clocksource/riscv_timer.c | 31 +++++++++++++++++++++++++++++++
>  2 files changed, 32 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/riscv/kernel/time.c b/arch/riscv/kernel/time.c
> index 1911c8f6..225fe743 100644
> --- a/arch/riscv/kernel/time.c
> +++ b/arch/riscv/kernel/time.c
> @@ -20,14 +20,7 @@ unsigned long riscv_timebase;
>  
>  void __init time_init(void)
>  {
> -	struct device_node *cpu;
> -	u32 prop;
> -
> -	cpu = of_find_node_by_path("/cpus");
> -	if (!cpu || of_property_read_u32(cpu, "timebase-frequency", &prop))
> -		panic(KERN_WARNING "RISC-V system with no 'timebase-frequency' in DTS\n");
> -	riscv_timebase = prop;
> +	timer_probe();
>  
>  	lpj_fine = riscv_timebase / HZ;
> -	timer_probe();
>  }
> diff --git a/drivers/clocksource/riscv_timer.c b/drivers/clocksource/riscv_timer.c
> index 084e97dc..75262409 100644
> --- a/drivers/clocksource/riscv_timer.c
> +++ b/drivers/clocksource/riscv_timer.c
> @@ -83,6 +83,35 @@ void riscv_timer_interrupt(void)
>  	evdev->event_handler(evdev);
>  }
>  
> +static void __init riscv_timebase_frequency(struct device_node *node,
> +					    int hartid)
> +{
> +	u32 timebase;
> +
> +	if (!of_property_read_u32(node, "timebase-frequency", &timebase))
> +		goto check;
> +
> +	/*
> +	 * As per the DT specification, timebase-frequency should be present
> +	 * under individual cpu node. Unfortunately, there are already available
> +	 * HiFive Unleashed devices where the timebase-frequency entry is under
> +	 * CPUs. check under parent "cpus" node to cover those devices.
> +	 */
> +	if (!of_property_read_u32(node->parent, "timebase-frequency",
> +				  &timebase))
> +		goto check;
> +
> +	panic("RISC-V system with no timebase-frequency in DTS for hart [%d]\n",
> +	      hartid);

no panic in the driver code please. Alternatively use pr_err and let the
timer-probe function spit the critical error on the console.

It would be nicer to add a fixed-clock and get the rate from it.

> +check:
> +	/* RISC-V ISA specification mandates that every cpu has a timer */
> +	if (!riscv_timebase)
> +		riscv_timebase = timebase;
> +	else if (riscv_timebase && riscv_timebase != timebase)
> +		pr_warn("RISC-V system with different timebase-frequency\n");
> +}
> +
>  static int __init riscv_timer_init_dt(struct device_node *n)
>  {
>  	int cpuid, hartid, error;
> @@ -90,10 +119,12 @@ static int __init riscv_timer_init_dt(struct device_node *n)
>  
>  	hartid = riscv_of_processor_hartid(n);
>  	cpuid = riscv_hartid_to_cpuid(hartid);
> +	riscv_timebase_frequency(n, hartid);
>  
>  	if (cpuid != smp_processor_id())
>  		return 0;

Somehow related to this change. Are you sure the test above makes sense?

> +	/* This should be called only for boot cpu */
>  	cs = per_cpu_ptr(&riscv_clocksource, cpuid);
>  	clocksource_register_hz(cs, riscv_timebase);
>  
> 


-- 
 <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH v2 1/4] dt-bindings: Correct RISC-V's timebase-frequency
  2018-12-14  9:17   ` Daniel Lezcano
@ 2019-01-04  0:36     ` Palmer Dabbelt
  2019-01-07  8:56       ` Daniel Lezcano
  0 siblings, 1 reply; 9+ messages in thread
From: Palmer Dabbelt @ 2019-01-04  0:36 UTC (permalink / raw)
  To: daniel.lezcano
  Cc: mark.rutland, devicetree, Damien.LeMoal, aou, dmitriy, anup,
	linux-kernel, Christoph Hellwig, atish.patra, robh+dt, tglx,
	linux-riscv, Christoph Hellwig

On Fri, 14 Dec 2018 01:17:24 PST (-0800), daniel.lezcano@linaro.org wrote:
> On 14/12/2018 00:14, Atish Patra wrote:
>> From: Palmer Dabbelt <palmer@sifive.com>
>>
>> In RISC-V systems, timebase-frequency is per cpu instead of one
>> instance for entire SOC as there is a individual timer per each CPU.
>> Fix the DT binding accordingly.
>
> Why not use a fixed-clock instead of this timebase property which forces
> to declare a global variable to be exported from arch/riscv to
> drivers/clocksource ?

That makes sense to me.  I've always disliked this global variable and a big 
part of why my original version got delayed forever is that I'd hoped to get 
rid of it.

Given that this is all a mess anyway I'm OK breaking backwards compatibility 
here.

Is there an example of how to do this?

> In addition, please add the 'Fixes' tag
>
>> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
>> Signed-off-by: Christoph Hellwig <hch@lst.de>
>> [Atish: Update the commit text]
>> Signed-off-by: Atish Patra <atish.patra@wdc.com>
>> Reviewed-by: Rob Herring <robh@kernel.org>
>> ---
>>  Documentation/devicetree/bindings/riscv/cpus.txt | 4 +++-
>>  1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt
>> index adf7b7af..b0b038d6 100644
>> --- a/Documentation/devicetree/bindings/riscv/cpus.txt
>> +++ b/Documentation/devicetree/bindings/riscv/cpus.txt
>> @@ -93,9 +93,9 @@ Linux is allowed to run on.
>>          cpus {
>>                  #address-cells = <1>;
>>                  #size-cells = <0>;
>> -                timebase-frequency = <1000000>;
>>                  cpu@0 {
>>                          clock-frequency = <1600000000>;
>> +                        timebase-frequency = <1000000>;
>>                          compatible = "sifive,rocket0", "riscv";
>>                          device_type = "cpu";
>>                          i-cache-block-size = <64>;
>> @@ -113,6 +113,7 @@ Linux is allowed to run on.
>>                  };
>>                  cpu@1 {
>>                          clock-frequency = <1600000000>;
>> +                        timebase-frequency = <1000000>;
>>                          compatible = "sifive,rocket0", "riscv";
>>                          d-cache-block-size = <64>;
>>                          d-cache-sets = <64>;
>> @@ -145,6 +146,7 @@ Example: Spike ISA Simulator with 1 Hart
>>  This device tree matches the Spike ISA golden model as run with `spike -p1`.
>>
>>          cpus {
>> +                timebase-frequency = <1000000>;
>>                  cpu@0 {
>>                          device_type = "cpu";
>>                          reg = <0x00000000>;

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH v2 1/4] dt-bindings: Correct RISC-V's timebase-frequency
  2019-01-04  0:36     ` Palmer Dabbelt
@ 2019-01-07  8:56       ` Daniel Lezcano
  0 siblings, 0 replies; 9+ messages in thread
From: Daniel Lezcano @ 2019-01-07  8:56 UTC (permalink / raw)
  To: Palmer Dabbelt
  Cc: mark.rutland, devicetree, Damien.LeMoal, aou, dmitriy, anup,
	linux-kernel, Christoph Hellwig, atish.patra, robh+dt, tglx,
	linux-riscv, Christoph Hellwig

On 04/01/2019 01:36, Palmer Dabbelt wrote:
> On Fri, 14 Dec 2018 01:17:24 PST (-0800), daniel.lezcano@linaro.org wrote:
>> On 14/12/2018 00:14, Atish Patra wrote:
>>> From: Palmer Dabbelt <palmer@sifive.com>
>>>
>>> In RISC-V systems, timebase-frequency is per cpu instead of one
>>> instance for entire SOC as there is a individual timer per each CPU.
>>> Fix the DT binding accordingly.
>>
>> Why not use a fixed-clock instead of this timebase property which forces
>> to declare a global variable to be exported from arch/riscv to
>> drivers/clocksource ?
> 
> That makes sense to me.  I've always disliked this global variable and a
> big part of why my original version got delayed forever is that I'd
> hoped to get rid of it.
> 
> Given that this is all a mess anyway I'm OK breaking backwards
> compatibility here.
> 
> Is there an example of how to do this?


Can you give some hardware details? Is the timebase frequency constant?
If it is the case, a fixed-clock shared for each cpu can be used, no?

    myclock: myclock {
        compatible = "fixed-clock";
        #clock-cells = <0>;
        clock-frequency  = <1000000>;
        clock-output-names = "mytimer";
    };

Alternatively, may be different output can be specified with the clock,
one for each CPUs.

Or if the timebase frequency is resulting from a clock divisor, it can
be defined as:

        clock {
                compatible = "fixed-factor-clock";
                clocks = <&parentclk>;
                #clock-cells = <0>;
                clock-div = <2>;
                clock-mult = <1>;
        };

hardware details can help to narrow down the right description.


>> In addition, please add the 'Fixes' tag
>>
>>> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
>>> Signed-off-by: Christoph Hellwig <hch@lst.de>
>>> [Atish: Update the commit text]
>>> Signed-off-by: Atish Patra <atish.patra@wdc.com>
>>> Reviewed-by: Rob Herring <robh@kernel.org>
>>> ---
>>>  Documentation/devicetree/bindings/riscv/cpus.txt | 4 +++-
>>>  1 file changed, 3 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt
>>> b/Documentation/devicetree/bindings/riscv/cpus.txt
>>> index adf7b7af..b0b038d6 100644
>>> --- a/Documentation/devicetree/bindings/riscv/cpus.txt
>>> +++ b/Documentation/devicetree/bindings/riscv/cpus.txt
>>> @@ -93,9 +93,9 @@ Linux is allowed to run on.
>>>          cpus {
>>>                  #address-cells = <1>;
>>>                  #size-cells = <0>;
>>> -                timebase-frequency = <1000000>;
>>>                  cpu@0 {
>>>                          clock-frequency = <1600000000>;
>>> +                        timebase-frequency = <1000000>;
>>>                          compatible = "sifive,rocket0", "riscv";
>>>                          device_type = "cpu";
>>>                          i-cache-block-size = <64>;
>>> @@ -113,6 +113,7 @@ Linux is allowed to run on.
>>>                  };
>>>                  cpu@1 {
>>>                          clock-frequency = <1600000000>;
>>> +                        timebase-frequency = <1000000>;
>>>                          compatible = "sifive,rocket0", "riscv";
>>>                          d-cache-block-size = <64>;
>>>                          d-cache-sets = <64>;
>>> @@ -145,6 +146,7 @@ Example: Spike ISA Simulator with 1 Hart
>>>  This device tree matches the Spike ISA golden model as run with
>>> `spike -p1`.
>>>
>>>          cpus {
>>> +                timebase-frequency = <1000000>;
>>>                  cpu@0 {
>>>                          device_type = "cpu";
>>>                          reg = <0x00000000>;


-- 
 <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 9+ messages in thread

end of thread, back to index

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-12-13 23:14 [PATCH v2 0/4] Timer code cleanup Atish Patra
2018-12-13 23:14 ` [PATCH v2 1/4] dt-bindings: Correct RISC-V's timebase-frequency Atish Patra
2018-12-14  9:17   ` Daniel Lezcano
2019-01-04  0:36     ` Palmer Dabbelt
2019-01-07  8:56       ` Daniel Lezcano
2018-12-13 23:14 ` [PATCH v2 2/4] RISC-V: Support per-hart timebase-frequency Atish Patra
2018-12-14  9:24   ` Daniel Lezcano
2018-12-13 23:14 ` [PATCH v2 3/4] RISC-V: Remove per cpu clocksource Atish Patra
2018-12-13 23:14 ` [PATCH v2 4/4] RISC-V: Fix non-smp kernel boot on SMP systems Atish Patra

Linux-RISC-V Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-riscv/0 linux-riscv/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-riscv linux-riscv/ https://lore.kernel.org/linux-riscv \
		linux-riscv@lists.infradead.org infradead-linux-riscv@archiver.kernel.org
	public-inbox-index linux-riscv


Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.infradead.lists.linux-riscv


AGPL code for this site: git clone https://public-inbox.org/ public-inbox