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[88.156.142.67]) by smtp.gmail.com with ESMTPSA id z25-20020a195e59000000b004aa14caf6e9sm577178lfi.58.2022.11.25.07.55.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 25 Nov 2022 07:55:13 -0800 (PST) Message-ID: Date: Fri, 25 Nov 2022 16:55:11 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Subject: Re: [PATCH v4 6/7] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Content-Language: en-US To: Conor Dooley Cc: "Lad, Prabhakar" , Paul Walmsley , Palmer Dabbelt , Albert Ou , Geert Uytterhoeven , Magnus Damm , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Guo Ren , Jisheng Zhang , Atish Patra , Anup Patel , Andrew Jones , Nathan Chancellor , Philipp Tomsich , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Biju Das , Lad Prabhakar References: <20221124172207.153718-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221124172207.153718-7-prabhakar.mahadev-lad.rj@bp.renesas.com> <70d1bfde-f57f-1741-08d3-23e362793595@linaro.org> <9b0f8312-2caa-b9f3-edf3-1b720532f559@linaro.org> From: Krzysztof Kozlowski In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221125_075517_701274_46BF1393 X-CRM114-Status: GOOD ( 21.27 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 25/11/2022 13:25, Conor Dooley wrote: > On Fri, Nov 25, 2022 at 01:12:18PM +0100, Krzysztof Kozlowski wrote: >> On 25/11/2022 11:34, Lad, Prabhakar wrote: >>>>> +/* Device, Non-bufferable */ >>>>> +#define AX45MP_PMACFG_MTYP_DEV_NON_BUF (0 << 2) >>>>> +/* Device, bufferable */ >>>>> +#define AX45MP_PMACFG_MTYP_DEV_BUF (1 << 2) >>>>> +/* Memory, Non-cacheable, Non-bufferable */ >>>>> +#define AX45MP_PMACFG_MTYP_MEM_NON_CACHE_NON_BUF (2 << 2) >>>>> +/* Memory, Non-cacheable, Bufferable */ >>>>> +#define AX45MP_PMACFG_MTYP_MEM_NON_CACHE_BUF (3 << 2) >>>> >>>> What are all these? They don't look like flags, because 3 = 1 | 2... >>>> they don't look like constants, because we do not use shifts in >>>> constants. Are these some register values? I also do not see the header >>>> being used in the code, so why having a bindings header if it is not >>>> used (DTS is not usage...)? >>>> >>> These are register bit values for the MTYP[5:2] field. The DTS example >>> in the binding doc (above) uses these macros. I haven't included the >>> DTS/I patches with this patchset yet do think I should? >> >> Then why storing it as bindings? Bindings headers describe the interface >> implemented by drivers and used by DTS, but this is not implemented by >> drivers. > > IIUC, some of these properties are non-discoverable attributes of the > cache controller. I see two things that could be done here that are > "better" than #defining bits: I did not comment about properties. I comment about constants. Why register values/offsets/addresses are in this particular case suitable for binding headers? > - add an RZ/Five specific compatible and use match data to set the > attributes which is only possible if the pma-regions are set on a > per SoC basis > - make pma-regions into a child node, in which andestech,non-cacheable > andestech,non-bufferable etc are properties of the child node > > Prabhakar, does that make sense or am I off with my understanding of the > attributes? Best regards, Krzysztof _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv