From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,URIBL_SBL,URIBL_SBL_A,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C169C43331 for ; Tue, 12 Nov 2019 10:39:16 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1A1CF206BA for ; Tue, 12 Nov 2019 10:39:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="lC4md6mC" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1A1CF206BA Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=linutronix.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:Message-ID: In-Reply-To:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=wvmx4+CGOVdfiZgo2ejEd9gNRKqjsvcLu3chkWnsgpk=; b=lC4md6mCWVhvfT x4O3L16lLVGdv6U8HqREzNVo5ILWs9ZDFE4v786/dt4gMMTfrttp8U9lHpxZicHajC/N9IOMn1A31 FU6GuxM0fTbaQUpcK10gUZIo/bmPX+sQclusRG8QBgSN4Q+CZGJv8NoAnHoaIHmwuIufKKsc0WojQ 1/TydAjAgAm6NQuHwQE/dywXOQJmcU2q+QOu/62gvgIIh96wX6NtHB45rjb9fxzT1XI7TlZADVfJG tovKblDCYZYZDi88vB5Mtx3XtrbPs21UfjbHgknBiFa4mo0Jx/OX/uEoN7n7yD5AfZZo8ltTbIhcG AOTEoyPMCRmTLvz3TdXQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iUTZr-0004h4-8Z; Tue, 12 Nov 2019 10:39:15 +0000 Received: from galois.linutronix.de ([2a0a:51c0:0:12e:550::1]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iUTZo-0004gL-DO for linux-riscv@lists.infradead.org; Tue, 12 Nov 2019 10:39:13 +0000 Received: from p5b06da22.dip0.t-ipconnect.de ([91.6.218.34] helo=nanos) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iUTZm-0007zU-0Z; Tue, 12 Nov 2019 11:39:10 +0100 Date: Tue, 12 Nov 2019 11:39:09 +0100 (CET) From: Thomas Gleixner To: Christoph Hellwig Subject: Re: [PATCH 06/12] riscv: add support for MMIO access to the timer registers In-Reply-To: <20191028121043.22934-7-hch@lst.de> Message-ID: References: <20191028121043.22934-1-hch@lst.de> <20191028121043.22934-7-hch@lst.de> User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1, SHORTCIRCUIT=-0.0001 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191112_023912_596672_9F4E0915 X-CRM114-Status: GOOD ( 12.94 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , Anup Patel , Palmer Dabbelt , linux-kernel@vger.kernel.org, Christoph Hellwig , Paul Walmsley , linux-riscv@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, 28 Oct 2019, Christoph Hellwig wrote: > When running in M-mode we can't use the SBI to set the timer, and > don't have access to the time CSR as that usually is emulated by > M-mode. Instead provide code that directly accesses the MMIO for > the timer. > > Signed-off-by: Christoph Hellwig > Reviewed-by: Anup Patel > --- > arch/riscv/include/asm/sbi.h | 3 ++- > arch/riscv/include/asm/timex.h | 19 +++++++++++++++++-- > drivers/clocksource/timer-riscv.c | 21 +++++++++++++++++---- Acked-by: Thomas Gleixner _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv