From: "Maciej W. Rozycki" <macro@orcam.me.uk>
To: Rob Herring <robh@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Stafford Horne <shorne@gmail.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Arnd Bergmann <arnd@arndb.de>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Guo Ren <guoren@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Richard Weinberger <richard@nod.at>,
Anton Ivanov <anton.ivanov@cambridgegreys.com>,
Johannes Berg <johannes@sipsolutions.net>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
linux-csky@vger.kernel.org,
linux-riscv <linux-riscv@lists.infradead.org>,
linux-um@lists.infradead.org, PCI <linux-pci@vger.kernel.org>,
"open list:GENERIC INCLUDE/ASM HEADER FILES"
<linux-arch@vger.kernel.org>
Subject: Re: [PATCH v3 2/2] asm-generic: Add new pci.h and use it
Date: Fri, 22 Jul 2022 23:28:05 +0100 (BST) [thread overview]
Message-ID: <alpine.DEB.2.21.2207222325010.48997@angie.orcam.me.uk> (raw)
In-Reply-To: <CAL_JsqK-_m2=yiD4qeSoXD-Uhh_r+kmC1qK50t8Tads-i+iJqw@mail.gmail.com>
On Fri, 22 Jul 2022, Rob Herring wrote:
> > > So again, how does one get a 0 address handed out when that's not even
> > > a valid region according to DT? Is there some legacy stuff that
> > > ignores the bridge windows?
> >
> > It doesn't matter as <asm/pci.h> just sets it as a generic parameter for
> > the platform, reflecting the limitation of PCI core, which in the course
> > of the discussion referred was found rather infeasible to remove. The
> > FU740 does not decode to PCI at 0, but another RISC-V device could. And I
> > think that DT should faithfully describe hardware and not our software
> > limitations.
>
> Let me ask this another way. When would a 0 memory or i/o address ever
> work? It doesn't seem this s/w limitation has anything specific to
> Risc-V. Given pci_iomap_range() rejects 0, I can't see how it could
> ever work. Maybe only for legacy ISA? So should the generic defaults
> just be what Risc-V is using instead of 0?
Absolutely, cf.:
<https://lore.kernel.org/lkml/alpine.DEB.2.21.2202260044180.25061@angie.orcam.me.uk/>.
Maciej
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next prev parent reply other threads:[~2022-07-22 22:28 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-18 0:41 [PATCH v3 0/2] Updates for asm-generic/pci.h Stafford Horne
2022-07-18 0:41 ` [PATCH v3 1/2] asm-generic: Remove pci.h copying remaining code to x86 Stafford Horne
2022-07-18 8:22 ` Geert Uytterhoeven
2022-07-19 12:02 ` Pierre Morel
2022-07-18 0:41 ` [PATCH v3 2/2] asm-generic: Add new pci.h and use it Stafford Horne
2022-07-19 15:58 ` Palmer Dabbelt
2022-07-21 22:05 ` Stafford Horne
2022-07-21 22:53 ` Palmer Dabbelt
2022-07-21 23:06 ` Rob Herring
2022-07-22 10:53 ` Arnd Bergmann
2022-07-22 15:27 ` Palmer Dabbelt
2022-07-22 16:36 ` Rob Herring
2022-07-22 19:23 ` Maciej W. Rozycki
2022-07-22 19:42 ` Rob Herring
2022-07-22 22:28 ` Maciej W. Rozycki [this message]
2022-07-22 19:55 ` Arnd Bergmann
2022-07-22 21:39 ` Jessica Clarke
2022-07-22 21:44 ` Rob Herring
2022-07-22 22:41 ` Maciej W. Rozycki
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