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* [PATCH v2] RISC-V: Add PCIe I/O BAR memory mapping
@ 2019-10-25  8:30 Yash Shah
  2019-10-25 15:53 ` Paul Walmsley
  0 siblings, 1 reply; 4+ messages in thread
From: Yash Shah @ 2019-10-25  8:30 UTC (permalink / raw)
  To: Paul Walmsley ( Sifive), Palmer Dabbelt ( Sifive),
	linux-riscv, linux-kernel
  Cc: sorear2, aou, alex, catalin.marinas, Anup.Patel, Yash Shah, rppt,
	Sachin Ghadi, logang, Greentime Hu, gregkh, tglx, will, allison

For legacy I/O BARs (non-MMIO BARs) to work correctly on RISC-V Linux,
we need to establish a reserved memory region for them, so that drivers
that wish to use the legacy I/O BARs can issue reads and writes against
a memory region that is mapped to the host PCIe controller's I/O BAR
mapping.

Signed-off-by: Yash Shah <yash.shah@sifive.com>
---

Changes in v2:
- update patch description as per Paul's suggestion
https://lore.kernel.org/linux-riscv/alpine.DEB.2.21.9999.1910240937350.20010@viisi.sifive.com/

---
 arch/riscv/include/asm/io.h      | 7 +++++++
 arch/riscv/include/asm/pgtable.h | 7 ++++++-
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index fc1189a..3ba4d93 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -13,6 +13,7 @@
 
 #include <linux/types.h>
 #include <asm/mmiowb.h>
+#include <asm/pgtable.h>
 
 extern void __iomem *ioremap(phys_addr_t offset, unsigned long size);
 
@@ -162,6 +163,12 @@ static inline u64 __raw_readq(const volatile void __iomem *addr)
 #endif
 
 /*
+ *  I/O port access constants.
+ */
+#define IO_SPACE_LIMIT		(PCI_IO_SIZE - 1)
+#define PCI_IOBASE		((void __iomem *)PCI_IO_START)
+
+/*
  * Emulation routines for the port-mapped IO space used by some PCI drivers.
  * These are defined as being "fully synchronous", but also "not guaranteed to
  * be fully ordered with respect to other memory and I/O operations".  We're
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 7fc5e4a..d78cc74 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -7,6 +7,7 @@
 #define _ASM_RISCV_PGTABLE_H
 
 #include <linux/mmzone.h>
+#include <linux/sizes.h>
 
 #include <asm/pgtable-bits.h>
 
@@ -88,6 +89,7 @@ extern pgd_t swapper_pg_dir[];
 #define VMALLOC_SIZE     (KERN_VIRT_SIZE >> 1)
 #define VMALLOC_END      (PAGE_OFFSET - 1)
 #define VMALLOC_START    (PAGE_OFFSET - VMALLOC_SIZE)
+#define PCI_IO_SIZE      SZ_16M
 
 /*
  * Roughly size the vmemmap space to be large enough to fit enough
@@ -102,7 +104,10 @@ extern pgd_t swapper_pg_dir[];
 
 #define vmemmap		((struct page *)VMEMMAP_START)
 
-#define FIXADDR_TOP      (VMEMMAP_START)
+#define PCI_IO_END       VMEMMAP_START
+#define PCI_IO_START     (PCI_IO_END - PCI_IO_SIZE)
+#define FIXADDR_TOP      PCI_IO_START
+
 #ifdef CONFIG_64BIT
 #define FIXADDR_SIZE     PMD_SIZE
 #else
-- 
2.7.4


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^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH v2] RISC-V: Add PCIe I/O BAR memory mapping
  2019-10-25  8:30 [PATCH v2] RISC-V: Add PCIe I/O BAR memory mapping Yash Shah
@ 2019-10-25 15:53 ` Paul Walmsley
  2019-10-29  4:19   ` Yash Shah
  0 siblings, 1 reply; 4+ messages in thread
From: Paul Walmsley @ 2019-10-25 15:53 UTC (permalink / raw)
  To: Yash Shah
  Cc: sorear2, aou, alex, catalin.marinas, Palmer Dabbelt \( Sifive\),
	Anup.Patel, linux-kernel, Paul Walmsley \( Sifive\),
	rppt, Sachin Ghadi, logang, Greentime Hu, gregkh, linux-riscv,
	will, tglx, allison

On Fri, 25 Oct 2019, Yash Shah wrote:

> For legacy I/O BARs (non-MMIO BARs) to work correctly on RISC-V Linux,
> we need to establish a reserved memory region for them, so that drivers
> that wish to use the legacy I/O BARs can issue reads and writes against
> a memory region that is mapped to the host PCIe controller's I/O BAR
> mapping.
> 
> Signed-off-by: Yash Shah <yash.shah@sifive.com>

Thanks.  And just to confirm: this is a fix, right?  Without this patch, 
legacy PCIe I/O resources won't be accessible on RISC-V?


- Paul

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http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 4+ messages in thread

* RE: [PATCH v2] RISC-V: Add PCIe I/O BAR memory mapping
  2019-10-25 15:53 ` Paul Walmsley
@ 2019-10-29  4:19   ` Yash Shah
  2019-10-29 18:22     ` Paul Walmsley
  0 siblings, 1 reply; 4+ messages in thread
From: Yash Shah @ 2019-10-29  4:19 UTC (permalink / raw)
  To: Paul Walmsley ( Sifive)
  Cc: logang, sorear2, aou, alex, gregkh, catalin.marinas,
	Palmer Dabbelt \( Sifive\),
	linux-kernel, rppt, Sachin Ghadi, Anup.Patel,
	Paul Walmsley \( Sifive\),
	Greentime Hu, linux-riscv, will, tglx, allison

> On Fri, 25 Oct 2019, Yash Shah wrote:
> 
> > For legacy I/O BARs (non-MMIO BARs) to work correctly on RISC-V Linux,
> > we need to establish a reserved memory region for them, so that
> > drivers that wish to use the legacy I/O BARs can issue reads and
> > writes against a memory region that is mapped to the host PCIe
> > controller's I/O BAR mapping.
> >
> > Signed-off-by: Yash Shah <yash.shah@sifive.com>
> 
> Thanks.  And just to confirm: this is a fix, right?  Without this patch, legacy
> PCIe I/O resources won't be accessible on RISC-V?

Yes, this is a fix.

- Yash

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 4+ messages in thread

* RE: [PATCH v2] RISC-V: Add PCIe I/O BAR memory mapping
  2019-10-29  4:19   ` Yash Shah
@ 2019-10-29 18:22     ` Paul Walmsley
  0 siblings, 0 replies; 4+ messages in thread
From: Paul Walmsley @ 2019-10-29 18:22 UTC (permalink / raw)
  To: Yash Shah
  Cc: sorear2, aou, catalin.marinas, alex, gregkh,
	Palmer Dabbelt \\\( Sifive\\\),
	will, linux-kernel, rppt, Sachin Ghadi, Anup.Patel,
	Paul Walmsley \( Sifive\),
	Greentime Hu, linux-riscv, logang, tglx, allison

On Tue, 29 Oct 2019, Yash Shah wrote:

> > On Fri, 25 Oct 2019, Yash Shah wrote:
> > 
> > > For legacy I/O BARs (non-MMIO BARs) to work correctly on RISC-V Linux,
> > > we need to establish a reserved memory region for them, so that
> > > drivers that wish to use the legacy I/O BARs can issue reads and
> > > writes against a memory region that is mapped to the host PCIe
> > > controller's I/O BAR mapping.
> > >
> > > Signed-off-by: Yash Shah <yash.shah@sifive.com>
> > 
> > Thanks.  And just to confirm: this is a fix, right?  Without this 
> > patch, legacy PCIe I/O resources won't be accessible on RISC-V?
> 
> Yes, this is a fix.

Thanks, queued for v5.4-rc.


- Paul

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 4+ messages in thread

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2019-10-25  8:30 [PATCH v2] RISC-V: Add PCIe I/O BAR memory mapping Yash Shah
2019-10-25 15:53 ` Paul Walmsley
2019-10-29  4:19   ` Yash Shah
2019-10-29 18:22     ` Paul Walmsley

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