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[75.161.11.128]) by smtp.gmail.com with ESMTPSA id u6sm4457439iop.18.2019.09.06.15.33.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Sep 2019 15:33:03 -0700 (PDT) Date: Fri, 6 Sep 2019 15:33:02 -0700 (PDT) From: Paul Walmsley X-X-Sender: paulw@viisi.sifive.com To: Christoph Hellwig Subject: Re: [PATCH] riscv: move sifive_l2_cache.c to drivers/soc In-Reply-To: <20190819062619.GA20211@lst.de> Message-ID: References: <20190818082935.14869-1-hch@lst.de> <20190819060904.GA4841@zn.tnic> <20190819062619.GA20211@lst.de> User-Agent: Alpine 2.21.9999 (DEB 301 2018-08-15) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190906_153308_850662_CB076A2C X-CRM114-Status: GOOD ( 14.86 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@sifive.com, linux-kernel@vger.kernel.org, Yash Shah , Borislav Petkov , linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, 19 Aug 2019, Christoph Hellwig wrote: > On Mon, Aug 19, 2019 at 08:09:04AM +0200, Borislav Petkov wrote: > > On Sun, Aug 18, 2019 at 10:29:35AM +0200, Christoph Hellwig wrote: > > > The sifive_l2_cache.c is in no way related to RISC-V architecture > > > memory management. It is a little stub driver working around the fact > > > that the EDAC maintainers prefer their drivers to be structured in a > > > certain way > > > > That changed recently so I guess we can do the per-IP block driver after > > all, if people would still prefer it. > > That would seem like the best idea. But I don't really know this code > well enough myself, and I really need to get this code out of the > forced on RISC-V codebase as some SOCs I'm working with simply don't > have the memory for it.. If that's your primary concern, then in the short term, how about just sending a single-line patch to the arch/riscv/mm Makefile to skip building it if !CONFIG_SOC_SIFIVE? Assuming, that is, you won't be enabling EDAC support for those low-end SoCs. Then you won't need to get the ack from the EDAC folks in the short term. Then a patch to make the SiFive platform EDAC driver build contingent on CONFIG_SOC_SIFIVE could be sent separately. - Paul _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv