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Fri, 27 Sep 2019 11:25:13 -0700 (PDT) Date: Fri, 27 Sep 2019 11:25:13 -0700 (PDT) From: Paul Walmsley X-X-Sender: paulw@viisi.sifive.com To: torvalds@linux-foundation.org Subject: [GIT PULL] RISC-V additional updates for v5.4-rc1 Message-ID: User-Agent: Alpine 2.21.9999 (DEB 301 2018-08-15) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190927_112516_383433_D0D06EE4 X-CRM114-Status: GOOD ( 11.00 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org Linus, The following changes since commit b41dae061bbd722b9d7fa828f35d22035b218e18: Merge tag 'xfs-5.4-merge-7' of git://git.kernel.org/pub/scm/fs/xfs/xfs-linux (2019-09-18 18:32:43 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv/for-v5.4-rc1-b for you to fetch changes up to c82dd6d078a2bb29d41eda032bb96d05699a524d: riscv: Avoid interrupts being erroneously enabled in handle_exception() (2019-09-20 08:42:34 -0700) ---------------------------------------------------------------- RISC-V additional updates for v5.4-rc1 Some additional RISC-V updates for v5.4-rc1. This includes one significant fix: - Prevent interrupts from being unconditionally re-enabled during exception handling if they were disabled in the context in which the exception occurred Also a few other fixes: - Fix a build error when sparse memory support is manually enabled - Prevent CPUs beyond CONFIG_NR_CPUS from being enabled in early boot And a few minor improvements: - DT improvements: in the FU540 SoC DT files, improve U-Boot compatibility by adding an "ethernet0" alias, drop an unnecessary property from the DT files, and add support for the PWM device - KVM preparation: add a KVM-related macro for future RISC-V KVM support, and export some symbols required to build KVM support as modules - defconfig additions: build more drivers by default for QEMU configurations ---------------------------------------------------------------- Anup Patel (2): RISC-V: Enable VIRTIO drivers in RV64 and RV32 defconfig KVM: RISC-V: Add KVM_REG_RISCV for ONE_REG interface Atish Patra (1): RISC-V: Export kernel symbols for kvm Bin Meng (2): riscv: dts: sifive: Add ethernet0 to the aliases node riscv: dts: sifive: Drop "clock-frequency" property of cpu nodes Greentime Hu (1): RISC-V: Fix building error when CONFIG_SPARSEMEM_MANUAL=y Vincent Chen (1): riscv: Avoid interrupts being erroneously enabled in handle_exception() Xiang Wang (1): arch/riscv: disable excess harts before picking main boot hart Yash Shah (1): riscv: dts: Add DT support for SiFive FU540 PWM driver arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 22 +++++++++++++++++--- .../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 8 ++++++++ arch/riscv/configs/defconfig | 11 ++++++++++ arch/riscv/configs/rv32_defconfig | 11 ++++++++++ arch/riscv/include/asm/pgtable.h | 24 +++++++++++----------- arch/riscv/kernel/entry.S | 6 +++++- arch/riscv/kernel/head.S | 8 +++++--- arch/riscv/kernel/smp.c | 1 + arch/riscv/kernel/time.c | 1 + include/uapi/linux/kvm.h | 1 + 10 files changed, 74 insertions(+), 19 deletions(-) _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv