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In-Reply-To: <20191009085313.GA14021@andestech.com> Message-ID: References: <20191009085313.GA14021@andestech.com> User-Agent: Alpine 2.21.9999 (DEB 301 2018-08-15) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191016_115602_881319_D7C3BAC6 X-CRM114-Status: UNSURE ( 8.99 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-riscv@lists.infradead.org, palmer@sifive.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org Hi Alan, On Wed, 9 Oct 2019, Alan Kao wrote: > In arch/riscv/include/asm/tlbflush.h, the comment says > > > Flush entire local TLB. 'sfence.vma' implicitly fences with the instruction > > cache as well, so a 'fence.i' is not necessary. > > and in the privileged spec, it is stated that > > > Executing an SFENCE.VMA instruction guarantees that any previous stores > > already visible to the current RISC-V hart are ordered before all subsequent > > implicit references from that hart to the memory-management data structures. > > So my question is straightforward. Is I-cache a kind of memory-management data > structure? am I missing something here? > > Thanks for any clarification. We just had a discussion about this with Andrew. He clarified that SFENCE.VMA does not imply a FENCE.I, and we concluded that the comment in tlbflush.h is more confusing than helpful. So we'll remove it: https://lore.kernel.org/linux-riscv/alpine.DEB.2.21.9999.1910141254360.12988@viisi.sifive.com/T/#u Thanks for bringing this up, - Paul _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv